From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1L2ZvK-0000G1-3O for qemu-devel@nongnu.org; Tue, 18 Nov 2008 18:23:58 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1L2ZvI-0000Ce-7r for qemu-devel@nongnu.org; Tue, 18 Nov 2008 18:23:57 -0500 Received: from [199.232.76.173] (port=49980 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1L2ZvH-0000CS-W1 for qemu-devel@nongnu.org; Tue, 18 Nov 2008 18:23:56 -0500 Received: from mail.codesourcery.com ([65.74.133.4]:53000) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1L2ZvI-0008R3-1d for qemu-devel@nongnu.org; Tue, 18 Nov 2008 18:23:56 -0500 From: Paul Brook Subject: Re: [Qemu-devel] Re: [PATCH v5 18/18] gdbstub: x86: Switch 64/32 bit registers dynamically Date: Tue, 18 Nov 2008 23:23:51 +0000 References: <20081117161857.26880.45423.stgit@mchn012c.ww002.siemens.net> <200811182246.54653.paul@codesourcery.com> <49234ABB.90303@web.de> In-Reply-To: <49234ABB.90303@web.de> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200811182323.52357.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Jan Kiszka On Tuesday 18 November 2008, Jan Kiszka wrote: > Paul Brook wrote: > >> The best approach, definitely, would be to teach GDB how to switch the > >> disassembler mode depending on the thread's (or VCPUs) state. But so > >> there is neither a mechanism in GDB for this, nor is GDB even aware of > >> the x86 modes (no tracking of privileged registers). We have some > >> preliminary patches for this, but they are still far away from GDB > >> mainline. > > > > I'm pretty sure all the infrastructure is there. gdb is able to natively > > debug 32-bit binaries on a 64-bit host and is able to switch disassembler > > modes for ARM vs. Thumb. > > How is it done on ARM? Maybe that will provide the right pointer for x86. Anything you have symbols for you know what type of code it is from the binary. On ARM there's an EABI defined scheme for identifying arm/thumb/data regions. On x86 the ELF class of the image is probably sufficient. In the absence of real information gdb falls back to the current CPU mode, which is a bit in the CPU status register. Exactly which register/bit depends whether you're talking to an M-profile device. M-profile cores are identified based on the XML register descriptions. If you don't have an XML capable target then you don't get to debug M-profile devices. IIRC There's also a gdb option to override the fallback mode. Paul