From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1L8tsM-0007XP-Vz for qemu-devel@nongnu.org; Sat, 06 Dec 2008 04:55:03 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1L8tsL-0007WJ-56 for qemu-devel@nongnu.org; Sat, 06 Dec 2008 04:55:02 -0500 Received: from [199.232.76.173] (port=59771 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1L8tsL-0007WG-0T for qemu-devel@nongnu.org; Sat, 06 Dec 2008 04:55:01 -0500 Received: from 42.mail-out.ovh.net ([213.251.189.42]:59806) by monty-python.gnu.org with smtp (Exim 4.60) (envelope-from ) id 1L8tsK-0001Ub-DX for qemu-devel@nongnu.org; Sat, 06 Dec 2008 04:55:00 -0500 Date: Sat, 6 Dec 2008 10:44:01 +0100 From: Jean-Christophe PLAGNIOL-VILLARD Subject: Re: [Qemu-devel] [PATCH] SH4: SCI improvement Message-ID: <20081206094401.GA2977@game.jcrosoft.org> References: <49296B95.4020707@juno.dti.ne.jp> <20081123222621.GC30647@game.jcrosoft.org> <492A3017.5010904@juno.dti.ne.jp> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="LQksG6bCIzRHxTLp" Content-Disposition: inline In-Reply-To: <492A3017.5010904@juno.dti.ne.jp> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org --LQksG6bCIzRHxTLp Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On 13:39 Mon 24 Nov , Shin-ichiro KAWASAKI wrote: > Hi, Jean-san! > > It seems a good idea to make u-boot run on SH4-QEMU, > for brushing up SH4 emulation. > > Jean-Christophe PLAGNIOL-VILLARD wrote: >> I've add the flash support at 0xA0000000 >> and have qemu refusing to boot from it >> qemu: fatal: Trying to execute code outside RAM or ROM at 0xa000000A > >> I've also try to boot u-boot as a kernel and have the output working >> but not the input. Impossible to type anything > > I'm afraid that I have no idea about these two points now. > I just guess MMU emulation and SCIF emulation might not be enough to run u-boot. > > To investigate them more closely, I downloaded current u-boot git repository, > build if for r2d, and run u-boot.bin with -kernel option. But u-boot couldn't > boot with assertion failures. Following two parts caused them. > > - MMUCR initialization with 16 bit word write causes failure. > QEMU only implements 32 bit write for it, following SH7750 document. > - BSC's PCR access cause failure. QEMU does not implement it yet. > > Have you handled them? > you need to apply 1 patch on u-boot r2dplus fix register access I've send to the U-Boot ML and 2 patchs to qemu >>From you sh4: pci and mmu support and from I SH7750/51: add register BCR3, NCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support Best Regards, J. --LQksG6bCIzRHxTLp Content-Type: text/x-diff; charset=us-ascii Content-Disposition: attachment; filename="0001-r2dplus-fix-register-access.patch" >>From 54e5318dbc1beb1eb37843dc94331ce2d6d48f60 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 4 Dec 2008 13:24:00 +0100 Subject: [PATCH] r2dplus fix register access Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- board/renesas/r2dplus/lowlevel_init.S | 2 +- drivers/pci/pci_sh7751.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/board/renesas/r2dplus/lowlevel_init.S b/board/renesas/r2dplus/lowlevel_init.S index 87e30c5..28d2b37 100644 --- a/board/renesas/r2dplus/lowlevel_init.S +++ b/board/renesas/r2dplus/lowlevel_init.S @@ -21,7 +21,7 @@ lowlevel_init: mov.l MMUCR_A,r1 mov.l MMUCR_D,r0 - mov.w r0,@r1 + mov.l r0,@r1 mov.l BCR1_A,r1 mov.l BCR1_D,r0 diff --git a/drivers/pci/pci_sh7751.c b/drivers/pci/pci_sh7751.c index e3a0ea0..df6d76f 100644 --- a/drivers/pci/pci_sh7751.c +++ b/drivers/pci/pci_sh7751.c @@ -187,8 +187,8 @@ int pci_sh7751_init(struct pci_controller *hose) /* Copy BSC registers into PCI BSC */ p4_out(inl(SH7751_BCR1), SH7751_PCIBCR1); - p4_out(inl(SH7751_BCR2), SH7751_PCIBCR2); - p4_out(inl(SH7751_BCR3), SH7751_PCIBCR3); + p4_out(inw(SH7751_BCR2), SH7751_PCIBCR2); + p4_out(inw(SH7751_BCR3), SH7751_PCIBCR3); p4_out(inl(SH7751_WCR1), SH7751_PCIWCR1); p4_out(inl(SH7751_WCR2), SH7751_PCIWCR2); p4_out(inl(SH7751_WCR3), SH7751_PCIWCR3); -- 1.5.6.5 --LQksG6bCIzRHxTLp--