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* [Qemu-devel] [PATCH] target-ppc: initialize MSR appropriately in user-mode
@ 2008-12-08 19:13 Nathan Froyd
  2008-12-10 15:06 ` Aurelien Jarno
  0 siblings, 1 reply; 2+ messages in thread
From: Nathan Froyd @ 2008-12-08 19:13 UTC (permalink / raw)
  To: qemu-devel

We shouldn't blindly initialize the floating-point bit in MSR; we should
only do so if the processor we're targetting supports floating-point.
We should also do the same thing with the Altivec and e500 bits.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>

diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index 6bffa06..1a4d69e 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -2905,7 +2905,13 @@ void cpu_ppc_reset (void *opaque)
     msr |= (target_ulong)1 << MSR_BE;
 #endif
 #if defined(CONFIG_USER_ONLY)
-    msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
+    /* Initialize MSR with appropriate instruction capabilities.  */
+    if (env->msr_mask & ((target_ulong)1 << MSR_FP))
+      msr |= (target_ulong)1 << MSR_FP;
+    if (env->msr_mask & ((target_ulong)1 << MSR_VR))
+      msr |= (target_ulong)1 << MSR_VR;
+    if (env->msr_mask & ((target_ulong)1 << MSR_SPE))
+      msr |= (target_ulong)1 << MSR_SPE;
     msr |= (target_ulong)1 << MSR_PR;
 #else
     env->nip = env->hreset_vector | env->excp_prefix;

^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [Qemu-devel] [PATCH] target-ppc: initialize MSR appropriately in user-mode
  2008-12-08 19:13 [Qemu-devel] [PATCH] target-ppc: initialize MSR appropriately in user-mode Nathan Froyd
@ 2008-12-10 15:06 ` Aurelien Jarno
  0 siblings, 0 replies; 2+ messages in thread
From: Aurelien Jarno @ 2008-12-10 15:06 UTC (permalink / raw)
  To: qemu-devel

On Mon, Dec 08, 2008 at 11:13:51AM -0800, Nathan Froyd wrote:
> We shouldn't blindly initialize the floating-point bit in MSR; we should
> only do so if the processor we're targetting supports floating-point.
> We should also do the same thing with the Altivec and e500 bits.
> 
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>

I have fixed the problem by applying two different patches, one to mask
the computed MSR with the MSR mask, and one to active Altivec and SPE.

Thanks for you work.

> diff --git a/target-ppc/helper.c b/target-ppc/helper.c
> index 6bffa06..1a4d69e 100644
> --- a/target-ppc/helper.c
> +++ b/target-ppc/helper.c
> @@ -2905,7 +2905,13 @@ void cpu_ppc_reset (void *opaque)
>      msr |= (target_ulong)1 << MSR_BE;
>  #endif
>  #if defined(CONFIG_USER_ONLY)
> -    msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
> +    /* Initialize MSR with appropriate instruction capabilities.  */
> +    if (env->msr_mask & ((target_ulong)1 << MSR_FP))
> +      msr |= (target_ulong)1 << MSR_FP;
> +    if (env->msr_mask & ((target_ulong)1 << MSR_VR))
> +      msr |= (target_ulong)1 << MSR_VR;
> +    if (env->msr_mask & ((target_ulong)1 << MSR_SPE))
> +      msr |= (target_ulong)1 << MSR_SPE;
>      msr |= (target_ulong)1 << MSR_PR;
>  #else
>      env->nip = env->hreset_vector | env->excp_prefix;
> 
> 
> 
> 

-- 
  .''`.  Aurelien Jarno	            | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   aurel32@debian.org         | aurelien@aurel32.net
   `-    people.debian.org/~aurel32 | www.aurel32.net

^ permalink raw reply	[flat|nested] 2+ messages in thread

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