From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LAQdf-0000Ng-Ek for qemu-devel@nongnu.org; Wed, 10 Dec 2008 10:06:11 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LAQdd-0000MF-H0 for qemu-devel@nongnu.org; Wed, 10 Dec 2008 10:06:10 -0500 Received: from [199.232.76.173] (port=53547 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LAQdc-0000Lv-VM for qemu-devel@nongnu.org; Wed, 10 Dec 2008 10:06:09 -0500 Received: from hall.aurel32.net ([88.191.82.174]:41489) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LAQdc-0007hu-BP for qemu-devel@nongnu.org; Wed, 10 Dec 2008 10:06:08 -0500 Received: from lneuilly-152-21-37-9.w193-253.abo.wanadoo.fr ([193.253.214.9] helo=volta.aurel32.net) by hall.aurel32.net with esmtpsa (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.63) (envelope-from ) id 1LAQdb-0008Ic-3h for qemu-devel@nongnu.org; Wed, 10 Dec 2008 16:06:07 +0100 Received: from aurel32 by volta.aurel32.net with local (Exim 4.69) (envelope-from ) id 1LAQda-0006sM-5r for qemu-devel@nongnu.org; Wed, 10 Dec 2008 16:06:06 +0100 Date: Wed, 10 Dec 2008 16:06:06 +0100 From: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH] target-ppc: initialize MSR appropriately in user-mode Message-ID: <20081210150606.GD19379@volta.aurel32.net> References: <20081208191351.GF26277@codesourcery.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <20081208191351.GF26277@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Mon, Dec 08, 2008 at 11:13:51AM -0800, Nathan Froyd wrote: > We shouldn't blindly initialize the floating-point bit in MSR; we should > only do so if the processor we're targetting supports floating-point. > We should also do the same thing with the Altivec and e500 bits. > > Signed-off-by: Nathan Froyd I have fixed the problem by applying two different patches, one to mask the computed MSR with the MSR mask, and one to active Altivec and SPE. Thanks for you work. > diff --git a/target-ppc/helper.c b/target-ppc/helper.c > index 6bffa06..1a4d69e 100644 > --- a/target-ppc/helper.c > +++ b/target-ppc/helper.c > @@ -2905,7 +2905,13 @@ void cpu_ppc_reset (void *opaque) > msr |= (target_ulong)1 << MSR_BE; > #endif > #if defined(CONFIG_USER_ONLY) > - msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ > + /* Initialize MSR with appropriate instruction capabilities. */ > + if (env->msr_mask & ((target_ulong)1 << MSR_FP)) > + msr |= (target_ulong)1 << MSR_FP; > + if (env->msr_mask & ((target_ulong)1 << MSR_VR)) > + msr |= (target_ulong)1 << MSR_VR; > + if (env->msr_mask & ((target_ulong)1 << MSR_SPE)) > + msr |= (target_ulong)1 << MSR_SPE; > msr |= (target_ulong)1 << MSR_PR; > #else > env->nip = env->hreset_vector | env->excp_prefix; > > > > -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net