From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LASud-0003XO-7Q for qemu-devel@nongnu.org; Wed, 10 Dec 2008 12:31:51 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LASua-0003W3-TO for qemu-devel@nongnu.org; Wed, 10 Dec 2008 12:31:49 -0500 Received: from [199.232.76.173] (port=53303 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LASua-0003W0-P2 for qemu-devel@nongnu.org; Wed, 10 Dec 2008 12:31:48 -0500 Received: from hall.aurel32.net ([88.191.82.174]:45221) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LASuZ-0004WL-Vf for qemu-devel@nongnu.org; Wed, 10 Dec 2008 12:31:48 -0500 Received: from lneuilly-152-21-37-9.w193-253.abo.wanadoo.fr ([193.253.214.9] helo=volta.aurel32.net) by hall.aurel32.net with esmtpsa (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.63) (envelope-from ) id 1LASuY-0004uo-Bl for qemu-devel@nongnu.org; Wed, 10 Dec 2008 18:31:46 +0100 Received: from aurel32 by volta.aurel32.net with local (Exim 4.69) (envelope-from ) id 1LASuX-0002Pf-HB for qemu-devel@nongnu.org; Wed, 10 Dec 2008 18:31:45 +0100 Date: Wed, 10 Dec 2008 18:31:45 +0100 From: Aurelien Jarno Subject: Re: [Qemu-devel] Re: Re: SH4: Implement FD bit Message-ID: <20081210173145.GE19379@volta.aurel32.net> References: <200812012022.02276.vladimir@codesourcery.com> <20081207224734.GD3591@volta.aurel32.net> <20081210091526.GA19379@volta.aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Wed, Dec 10, 2008 at 02:04:27PM +0300, Vladimir Prus wrote: > Aurelien Jarno wrote: > > > On Tue, Dec 09, 2008 at 07:36:19PM +0300, Vladimir Prus wrote: > >> Aurelien Jarno wrote: > >> > >> >> > >> >> SH4 manual say that if a floating point instruction is executed while > >> >> FD bit in the status register is 1, an exception should be raised. QEMU > >> >> presently does not do that, so the kernel does not initialize FP state > >> >> for any thread, nor does it save/restore FP state. The most apparent > >> >> consequence is that while recent gcc/libc expect double-precision mode > >> >> to be set by kernel, they run in single-precision mode, and all FP code > >> >> produces wrong values. > >> >> > >> >> This patch fixes this. It also fixes a couple of places where PC was > >> >> not updated before handling an exception, although both those places > >> >> deal with invalid instruction and don't lead to any user-visible bugs. > >> >> > >> >> - Volodya > >> > > >> > Thanks, applied. > >> > >> Thanks, but it looks like one bit of the patch somehow did not > >> make it into SVN. Specifically, this: > >> > >> @@ -504,6 +523,13 @@ static void _decode_opc(DisasContext * ctx) > >> } > >> } > >> > >> + /* The 0xfffd instruction is underfined, so we don't want to > >> + raise fpu disable exception on it. */ > >> + if (((ctx->opcode & 0xf000) == 0xf000) > >> + && (ctx->opcode != 0xfffd)) > >> + { > >> + CHECK_FPU_ENABLED > >> + } > >> > >> Is present in my post, and is not present in: > >> > >> http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5937 > >> > >> Maybe some merge issue? > > > > Yes I haven't seen that one hunk of the patch has been rejected, so I > > missed this part. I have just tried to merge it by hand, but it is not > > possible to apply it. It looks like the patch was not done against the > > current SVN. > > > > Care to resend it against the current SVN? > > Attached is the remaining bit of the patch, against fresh SVN. Actually I don't really like the idea of checking in the beginning of the decode function for all instructions if they are a FP instruction, and then checking if FPU is enabled. Given the number of instructions (or group of instructions) concerned is not really big, I have committed a patch that does the same by adding the check in each of the concerned instruction. -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net