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Date: Thu, 11 Dec 2008 22:16:17 +0100
From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Subject: Re: [Qemu-devel] SH: Improve the interrupt controller
Message-ID: <20081211211617.GC9520@game.jcrosoft.org>
References: <200812112252.17620.vladimir@codesourcery.com>
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To: qemu-devel@nongnu.org

On 22:52 Thu 11 Dec     , Vladimir Prus wrote:
> 
> This patch improves the intc implementation in these ways:
> 
>    - On interrupt, the priority mask in SSR is updated,
>      if OPM register tells it should be
>    - We check interrupt priority and compare it with
>      priority mask
>    - Priorities for IRL interrupts (which are fixed), are
>      assigned
>    - The ICR register is supported, and LVLMODE bit, which
>      controls if interrupt is automatically de-asserted,
>      is implemented
>    - A bug where handling of paired set mask / clear mask
>      registers was done backward is fixed
>    - A bug where enabling a group did not work was fixed.
I'll be better to split this patch in two on for the bug fix and one
for the improvements

IMHO your patch need some coding style cleanup also

Best Regards,
J.