From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LAqDv-0007bT-Tz for qemu-devel@nongnu.org; Thu, 11 Dec 2008 13:25:20 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LAqDu-0007b6-Ss for qemu-devel@nongnu.org; Thu, 11 Dec 2008 13:25:19 -0500 Received: from [199.232.76.173] (port=38065 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LAqDu-0007b3-Nu for qemu-devel@nongnu.org; Thu, 11 Dec 2008 13:25:18 -0500 Received: from mx20.gnu.org ([199.232.41.8]:4453) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LAqDu-0005JA-1g for qemu-devel@nongnu.org; Thu, 11 Dec 2008 13:25:18 -0500 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LAqDt-0004ay-0J for qemu-devel@nongnu.org; Thu, 11 Dec 2008 13:25:17 -0500 From: Vladimir Prus Date: Thu, 11 Dec 2008 21:25:17 +0300 MIME-Version: 1.0 Content-Type: Multipart/Mixed; boundary="Boundary-00=_NsVQJgH5yG86cbe" Message-Id: <200812112125.17181.vladimir@codesourcery.com> Subject: [Qemu-devel] SH: Add prefi, icbi, synco Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org --Boundary-00=_NsVQJgH5yG86cbe Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline This is the repost of my eariler patch: http://thread.gmane.org/gmane.comp.emulators.qemu/31389 In this version, the new instructions are recognized only on SH4A. - Volodya --Boundary-00=_NsVQJgH5yG86cbe Content-Type: text/x-diff; charset="iso 8859-15"; name="0002-SH-Add-prefi-icbi-synco.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="0002-SH-Add-prefi-icbi-synco.patch" =46rom 47f4b541c79259579f921c1662bd86d102829d67 Mon Sep 17 00:00:00 2001 =46rom: Vladimir Prus Date: Sat, 20 Sep 2008 21:07:34 +0400 Subject: [PATCH] SH: Add prefi, icbi, synco To: qemu-devel@nongnu.org X-KMail-Transport: CodeSourcery X-KMail-Identity: 901867920 * target-sh4/cpu.h (enum sh_features): New. (CPUSH4State): New field features. * target-sh4/translate.c (DisasContext): New field features. (sh4_def_t): New field features. (cpu_sh4_init): Initialize env->features. (_decode_opc): Handle prefi, icbi, and synco. (gen_intermediate_code_internal): Initialize ctx.features. =2D-- target-sh4/cpu.h | 7 +++++++ target-sh4/translate.c | 20 ++++++++++++++++++++ 2 files changed, 27 insertions(+), 0 deletions(-) diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index bcf326c..a0108b4 100644 =2D-- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -89,6 +89,10 @@ typedef struct tlb_t { =20 #define NB_MMU_MODES 2 =20 +enum sh_features { + SH_FEATURE_SH4A =3D 1, +}; + typedef struct CPUSH4State { int id; /* CPU model */ =20 @@ -113,6 +117,9 @@ typedef struct CPUSH4State { /* float point status register */ float_status fp_status; =20 + /* The features that we should emulate. See sh_features above. */ + uint32_t features; + /* Those belong to the specific unit (SH7750) but are handled here */ uint32_t mmucr; /* MMU control register */ uint32_t pteh; /* page table entry high register */ diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 8ba7c8b..d38e95f 100644 =2D-- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -49,6 +49,7 @@ typedef struct DisasContext { int memidx; uint32_t delayed_pc; int singlestep_enabled; + uint32_t features; } DisasContext; =20 #if defined(CONFIG_USER_ONLY) @@ -206,6 +207,7 @@ typedef struct { uint32_t pvr; uint32_t prr; uint32_t cvr; + uint32_t features; } sh4_def_t; =20 static sh4_def_t sh4_defs[] =3D { @@ -227,6 +229,7 @@ static sh4_def_t sh4_defs[] =3D { .pvr =3D 0x10300700, .prr =3D 0x00000200, .cvr =3D 0x71440211, + .features =3D SH_FEATURE_SH4A, }, }; =20 @@ -271,6 +274,7 @@ CPUSH4State *cpu_sh4_init(const char *cpu_model) env =3D qemu_mallocz(sizeof(CPUSH4State)); if (!env) return NULL; + env->features =3D def->features; cpu_exec_init(env); sh4_translate_init(); env->cpu_model_str =3D cpu_model; @@ -1562,6 +1566,21 @@ static void _decode_opc(DisasContext * ctx) return; case 0x0083: /* pref @Rn */ return; + case 0x00d3: /* prefi @Rn */ + if (ctx->features & SH_FEATURE_SH4A) + return; + else + break; + case 0x00e3: /* icbi @Rn */ + if (ctx->features & SH_FEATURE_SH4A) + return; + else + break; + case 0x00ab: /* synco */ + if (ctx->features & SH_FEATURE_SH4A) + return; + else + break; case 0x4024: /* rotcl Rn */ { TCGv tmp =3D tcg_temp_new(); @@ -1805,6 +1824,7 @@ gen_intermediate_code_internal(CPUState * env, Transl= ationBlock * tb, ctx.delayed_pc =3D -1; /* use delayed pc from env pointer */ ctx.tb =3D tb; ctx.singlestep_enabled =3D env->singlestep_enabled; + ctx.features =3D env->features; =20 #ifdef DEBUG_DISAS if (loglevel & CPU_LOG_TB_CPU) { =2D-=20 1.5.3.5 --Boundary-00=_NsVQJgH5yG86cbe--