From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LAqG5-00005J-Pt for qemu-devel@nongnu.org; Thu, 11 Dec 2008 13:27:33 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LAqG4-0008WP-KD for qemu-devel@nongnu.org; Thu, 11 Dec 2008 13:27:33 -0500 Received: from [199.232.76.173] (port=38168 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LAqG4-0008WC-15 for qemu-devel@nongnu.org; Thu, 11 Dec 2008 13:27:32 -0500 Received: from mx20.gnu.org ([199.232.41.8]:4487) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LAqG3-0005hu-Az for qemu-devel@nongnu.org; Thu, 11 Dec 2008 13:27:31 -0500 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LAqG2-0004ej-8C for qemu-devel@nongnu.org; Thu, 11 Dec 2008 13:27:30 -0500 From: Vladimir Prus Date: Thu, 11 Dec 2008 21:27:28 +0300 MIME-Version: 1.0 Content-Type: Multipart/Mixed; boundary="Boundary-00=_RuVQJjUjxJYPeMc" Message-Id: <200812112127.29115.vladimir@codesourcery.com> Subject: [Qemu-devel] SH: Implement MOVCO.L and MOVLI.L Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org --Boundary-00=_RuVQJjUjxJYPeMc Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline This patch implements a couple more instructions specific to SH4A. The patch includes a copy of their description from the manual. The only point worth noting is the LDST -- my copy of the manual does not explain it, but I was told by Paul Mundt that this is internal state of the processor not otherwise exposed. So, adding a new field in processor state seems reasonable. - Volodya --Boundary-00=_RuVQJjUjxJYPeMc Content-Type: text/x-diff; charset="iso 8859-15"; name="0003-SH-Implement-MOVCO.L-and-MOVLI.L.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="0003-SH-Implement-MOVCO.L-and-MOVLI.L.patch" =46rom db021cfa5ca5a170d9691910ab7450cc84dcaf97 Mon Sep 17 00:00:00 2001 =46rom: Vladimir Prus Date: Sun, 12 Oct 2008 19:36:22 +0400 Subject: [PATCH] SH: Implement MOVCO.L and MOVLI.L To: qemu-devel@nongnu.org X-KMail-Transport: CodeSourcery X-KMail-Identity: 901867920 * target-sh4/cpu.h (struct CPUSH4State): New field ldst. * target-sh4/helper.c (do_interrupt): Initialize ldst. * target-sh4/translate.c (cpu_ldst): New. (sh4_translate_init): Initialize cpu_ldst. (_decode_opc): Support MOVCO.L and MOVLI.L. =2D-- target-sh4/cpu.h | 2 ++ target-sh4/helper.c | 1 + target-sh4/translate.c | 35 ++++++++++++++++++++++++++++++++++- 3 files changed, 37 insertions(+), 1 deletions(-) diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index a0108b4..ae434d1 100644 =2D-- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -135,6 +135,8 @@ typedef struct CPUSH4State { uint32_t prr; /* Processor Revision Register */ uint32_t cvr; /* Cache Version Register */ =20 + uint32_t ldst; + CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */ tlb_t itlb[ITLB_SIZE]; /* instruction translation table */ void *intc_handle; diff --git a/target-sh4/helper.c b/target-sh4/helper.c index 882bc9c..61b668b 100644 =2D-- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -160,6 +160,7 @@ void do_interrupt(CPUState * env) env->spc =3D env->pc; env->sgr =3D env->gregs[15]; env->sr |=3D SR_BL | SR_MD | SR_RB; + env->ldst =3D 0; =20 if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { /* Branch instruction should be executed again before delay slot. = */ diff --git a/target-sh4/translate.c b/target-sh4/translate.c index d38e95f..ba9db14 100644 =2D-- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -72,7 +72,7 @@ static TCGv_ptr cpu_env; static TCGv cpu_gregs[24]; static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr; static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl; =2Dstatic TCGv cpu_pr, cpu_fpscr, cpu_fpul; +static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_ldst; static TCGv cpu_fregs[32]; =20 /* internal register indexes */ @@ -144,6 +144,8 @@ static void sh4_translate_init(void) cpu_delayed_pc =3D tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, delayed_pc), "_delayed_pc_"); + cpu_ldst =3D tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUState, ldst), "_ldst_"); =20 for (i =3D 0; i < 32; i++) cpu_fregs[i] =3D tcg_global_mem_new_i32(TCG_AREG0, @@ -1543,6 +1545,37 @@ static void _decode_opc(DisasContext * ctx) case 0x0029: /* movt Rn */ tcg_gen_andi_i32(REG(B11_8), cpu_sr, SR_T); return; + case 0x0073: + /* MOVCO.L=20 + LDST -> T + If (T =3D=3D 1) R0 -> (Rn) + 0 -> LDST + For now, do unconditional move. FIXME. =20 + */ =20 + if (ctx->features & SH_FEATURE_SH4A) { + int label =3D gen_new_label(); + gen_clr_t(); + tcg_gen_or_i32(cpu_sr, cpu_sr, cpu_ldst); + tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ldst, 0, label); + tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx); + gen_set_label(label); + tcg_gen_movi_i32(cpu_ldst, 0); + return; + } else + break; + case 0x0063: + /* MOVLI.L @Rm,R0=20 + 1 -> LDST + (Rm) -> R0 + When interrupt/exception + occurred 0 -> LDST + */ =20 + if (ctx->features & SH_FEATURE_SH4A) { + tcg_gen_movi_i32(cpu_ldst, 1); + tcg_gen_qemu_ld32s(REG(0), REG(B11_8), ctx->memidx); + return; + } else + break; case 0x0093: /* ocbi @Rn */ { TCGv dummy =3D tcg_temp_new(); =2D-=20 1.5.3.5 --Boundary-00=_RuVQJjUjxJYPeMc--