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Date: Sat, 13 Dec 2008 01:18:03 +0000
From: Stuart Brady <sdbrady@ntlworld.com>
Subject: Re: [Qemu-devel] [5949] target-ppc: memory load/store rework
Message-ID: <20081213011803.GC9457@miranda.arrow>
References: <E1L9kZm-0001Qw-HN@cvs.savannah.gnu.org>
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To: qemu-devel@nongnu.org
Cc: Aurelien Jarno <aurelien@aurel32.net>

On Mon, Dec 08, 2008 at 06:11:22PM +0000, Aurelien Jarno wrote:
> - Don't swap values twice for bit-reverse load/store functions
>   in little endian mode.

If I've read this correctly, it seems to me that we would still swap
twice on little endian hosts when when emulating little endian mode or
performing bit-reverse loads/stores.  Bit-reverse loads/stores under
little endian emulation on a little endian host would have actually
resulted in *three* byteswaps!

I'm not sure what the performance impact of this would be, but it's 
something that I've been wondering about while working on PA-RISC
emulation, which will also need to provide a little endian mode.

BTW, I'm wondering if it would be possible to optimise loads/stores with
a different endianness to the host on targets that require word aligned
addresses.  Instead of swapping bytes when loading/storing words,
addresses would be modified when loading/storing bytes.  For 32-bit
targets, what I'm suggesting is something similar to this (although I'm
not saying that the casting is a good idea!) :-

extern uint8_t memory[];

uint32_t ldul(target_ulong addr) {
  return *(uint32_t)&memory[addr];
}

uint32_t lduw(target_ulong addr) {
  return *(uint16_t)&memory[addr ^ 2];
}

uint32_t ldub(target_ulong addr) {
  return memory[addr ^ 3];
}

(It looks as though MIPS Magnum emulation might require something like
this for emulation of its big endian mode, anyway...)

Cheers,
-- 
Stuart Brady