From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LBiMs-0006dx-Cs for qemu-devel@nongnu.org; Sat, 13 Dec 2008 23:14:10 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LBiMq-0006bj-I9 for qemu-devel@nongnu.org; Sat, 13 Dec 2008 23:14:09 -0500 Received: from [199.232.76.173] (port=47033 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LBiMq-0006bb-A3 for qemu-devel@nongnu.org; Sat, 13 Dec 2008 23:14:08 -0500 Received: from mx20.gnu.org ([199.232.41.8]:8458) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LBiMq-0000ET-05 for qemu-devel@nongnu.org; Sat, 13 Dec 2008 23:14:08 -0500 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LBiMp-0005VE-4m for qemu-devel@nongnu.org; Sat, 13 Dec 2008 23:14:07 -0500 Date: Sat, 13 Dec 2008 20:14:03 -0800 From: Nathan Froyd Message-ID: <20081214041403.GG23471@codesourcery.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Subject: [Qemu-devel] [PATCH] target-ppc: add support for reading/writing spefscr Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org As well as reading/writing the CPU's idea of what spefscr is, this patch also adds support for reading/writing it in user mode. Signed-off-by: Nathan Froyd --- target-ppc/translate.c | 4 ++++ target-ppc/translate_init.c | 21 +++++++++++++++------ 2 files changed, 19 insertions(+), 6 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index e2d6f42..82f1b9c 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -69,6 +69,7 @@ static TCGv cpu_lr; static TCGv cpu_xer; static TCGv cpu_reserve; static TCGv_i32 cpu_fpscr; +static TCGv_i32 cpu_spefscr; static TCGv_i32 cpu_access_type; #include "gen-icount.h" @@ -152,6 +153,9 @@ void ppc_translate_init(void) cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, fpscr), "fpscr"); + cpu_spefscr = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUState, spe_fscr), "spefscr"); + cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, access_type), "access_type"); diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 0ce81ed..60838aa 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -434,6 +434,17 @@ static void spr_write_pir (void *opaque, int sprn, int gprn) } #endif +/* SPE specific registers */ +static void spr_read_spefscr (void *opaque, int gprn, int sprn) +{ + tcg_gen_mov_tl(cpu_gpr[gprn], cpu_spefscr); +} + +static void spr_write_spefscr (void *opaque, int sprn, int gprn) +{ + tcg_gen_mov_tl(cpu_spefscr, cpu_gpr[gprn]); +} + #if !defined(CONFIG_USER_ONLY) /* Callback used to write the exception vector base */ static void spr_write_excp_prefix (void *opaque, int sprn, int gprn) @@ -3995,10 +4006,9 @@ static void init_proc_e200 (CPUPPCState *env) /* Time base */ gen_tbl(env); gen_spr_BookE(env, 0x000000070000FFFFULL); - /* XXX : not implemented */ spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_spefscr, &spr_write_spefscr, + &spr_read_spefscr, &spr_write_spefscr, 0x00000000); /* Memory management */ gen_spr_BookE_FSL(env, 0x0000005D); @@ -4165,10 +4175,9 @@ static void init_proc_e500 (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_pir, 0x00000000); - /* XXX : not implemented */ spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_spefscr, &spr_write_spefscr, + &spr_read_spefscr, &spr_write_spefscr, 0x00000000); /* Memory management */ #if !defined(CONFIG_USER_ONLY) -- 1.6.0.5