From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LBoUh-0005Ke-4M for qemu-devel@nongnu.org; Sun, 14 Dec 2008 05:46:39 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LBoUg-0005Ir-7L for qemu-devel@nongnu.org; Sun, 14 Dec 2008 05:46:38 -0500 Received: from [199.232.76.173] (port=49748 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LBoUg-0005Ib-2A for qemu-devel@nongnu.org; Sun, 14 Dec 2008 05:46:38 -0500 Received: from hall.aurel32.net ([88.191.82.174]:44894) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LBoUf-0001FQ-EZ for qemu-devel@nongnu.org; Sun, 14 Dec 2008 05:46:37 -0500 Date: Sun, 14 Dec 2008 11:46:34 +0100 From: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH] target-ppc: add support for reading/writing spefscr Message-ID: <20081214104634.GH17729@volta.aurel32.net> References: <20081214041403.GG23471@codesourcery.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <20081214041403.GG23471@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Nathan Froyd Cc: qemu-devel@nongnu.org On Sat, Dec 13, 2008 at 08:14:03PM -0800, Nathan Froyd wrote: > As well as reading/writing the CPU's idea of what spefscr is, this patch > also adds support for reading/writing it in user mode. > > Signed-off-by: Nathan Froyd I am not sure it is worth mapping fpescr as a TCG register given that except load/store it will be only used in op_helper.c. Moreover I am sure that sooner or later we will need an helper to write it, as a write may change rounding mode or trigger an exception. I think it is better to use tcg_gen_ld_tl/tcg_gen_st_tl as it is already done for other SPE registers. > --- > target-ppc/translate.c | 4 ++++ > target-ppc/translate_init.c | 21 +++++++++++++++------ > 2 files changed, 19 insertions(+), 6 deletions(-) > > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index e2d6f42..82f1b9c 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -69,6 +69,7 @@ static TCGv cpu_lr; > static TCGv cpu_xer; > static TCGv cpu_reserve; > static TCGv_i32 cpu_fpscr; > +static TCGv_i32 cpu_spefscr; > static TCGv_i32 cpu_access_type; > > #include "gen-icount.h" > @@ -152,6 +153,9 @@ void ppc_translate_init(void) > cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0, > offsetof(CPUState, fpscr), "fpscr"); > > + cpu_spefscr = tcg_global_mem_new_i32(TCG_AREG0, > + offsetof(CPUState, spe_fscr), "spefscr"); > + > cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0, > offsetof(CPUState, access_type), "access_type"); > > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index 0ce81ed..60838aa 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -434,6 +434,17 @@ static void spr_write_pir (void *opaque, int sprn, int gprn) > } > #endif > > +/* SPE specific registers */ > +static void spr_read_spefscr (void *opaque, int gprn, int sprn) > +{ > + tcg_gen_mov_tl(cpu_gpr[gprn], cpu_spefscr); > +} > + > +static void spr_write_spefscr (void *opaque, int sprn, int gprn) > +{ > + tcg_gen_mov_tl(cpu_spefscr, cpu_gpr[gprn]); > +} > + > #if !defined(CONFIG_USER_ONLY) > /* Callback used to write the exception vector base */ > static void spr_write_excp_prefix (void *opaque, int sprn, int gprn) > @@ -3995,10 +4006,9 @@ static void init_proc_e200 (CPUPPCState *env) > /* Time base */ > gen_tbl(env); > gen_spr_BookE(env, 0x000000070000FFFFULL); > - /* XXX : not implemented */ > spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", > - SPR_NOACCESS, SPR_NOACCESS, > - &spr_read_generic, &spr_write_generic, > + &spr_read_spefscr, &spr_write_spefscr, > + &spr_read_spefscr, &spr_write_spefscr, > 0x00000000); > /* Memory management */ > gen_spr_BookE_FSL(env, 0x0000005D); > @@ -4165,10 +4175,9 @@ static void init_proc_e500 (CPUPPCState *env) > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_pir, > 0x00000000); > - /* XXX : not implemented */ > spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", > - SPR_NOACCESS, SPR_NOACCESS, > - &spr_read_generic, &spr_write_generic, > + &spr_read_spefscr, &spr_write_spefscr, > + &spr_read_spefscr, &spr_write_spefscr, > 0x00000000); > /* Memory management */ > #if !defined(CONFIG_USER_ONLY) > -- > 1.6.0.5 > > > > -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net