From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LCMeG-0000cM-1B for qemu-devel@nongnu.org; Mon, 15 Dec 2008 18:14:48 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LCMeF-0000ai-4V for qemu-devel@nongnu.org; Mon, 15 Dec 2008 18:14:47 -0500 Received: from [199.232.76.173] (port=32841 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LCMeE-0000aT-Tj for qemu-devel@nongnu.org; Mon, 15 Dec 2008 18:14:46 -0500 Received: from hall.aurel32.net ([88.191.82.174]:38438) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LCMeE-0001K4-AD for qemu-devel@nongnu.org; Mon, 15 Dec 2008 18:14:46 -0500 Date: Tue, 16 Dec 2008 00:14:42 +0100 From: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH 2/8] Rename ppc405_sdram_init() to ppc4xx_sdram_init() Message-ID: <20081215231442.GI8523@volta.aurel32.net> References: <96a638341e900e704a826b272eaa9d6be53a0a52.1229359102.git.hollisb@us.ibm.com> <449347543ebc8c146307e1c6c7095326751c0167.1229359102.git.hollisb@us.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <449347543ebc8c146307e1c6c7095326751c0167.1229359102.git.hollisb@us.ibm.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: kvm-ppc@vger.kernel.org On Mon, Dec 15, 2008 at 10:44:13AM -0600, Hollis Blanchard wrote: > The SDRAM controller is shared across almost all 405 and 440 embedded > processors, with some slight differences such as the sizes supported for each > memory bank. > > Rename only; no functional changes. > > Signed-off-by: Hollis Blanchard Thanks, applied. > --- > hw/ppc405_uc.c | 4 ++-- > hw/ppc4xx.h | 2 +- > hw/ppc4xx_devs.c | 2 +- > 3 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c > index 7e7fb38..9275416 100644 > --- a/hw/ppc405_uc.c > +++ b/hw/ppc405_uc.c > @@ -2230,7 +2230,7 @@ CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], > pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); > *picp = pic; > /* SDRAM controller */ > - ppc405_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init); > + ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init); > offset = 0; > for (i = 0; i < 4; i++) > offset += ram_sizes[i]; > @@ -2588,7 +2588,7 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], > *picp = pic; > /* SDRAM controller */ > /* XXX 405EP has no ECC interrupt */ > - ppc405_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init); > + ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init); > offset = 0; > for (i = 0; i < 2; i++) > offset += ram_sizes[i]; > diff --git a/hw/ppc4xx.h b/hw/ppc4xx.h > index 8c2878a..3b98662 100644 > --- a/hw/ppc4xx.h > +++ b/hw/ppc4xx.h > @@ -48,7 +48,7 @@ enum { > qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, > uint32_t dcr_base, int has_ssr, int has_vr); > > -void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks, > +void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks, > target_phys_addr_t *ram_bases, > target_phys_addr_t *ram_sizes, > int do_init); > diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c > index c6be2d6..2d27e23 100644 > --- a/hw/ppc4xx_devs.c > +++ b/hw/ppc4xx_devs.c > @@ -846,7 +846,7 @@ static void sdram_reset (void *opaque) > sdram_unmap_bcr(sdram); > } > > -void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks, > +void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks, > target_phys_addr_t *ram_bases, > target_phys_addr_t *ram_sizes, > int do_init) > -- > 1.5.6.5 > > > > -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net