From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LCfxM-0006lb-Va for qemu-devel@nongnu.org; Tue, 16 Dec 2008 14:51:49 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LCfxI-0006ku-DT for qemu-devel@nongnu.org; Tue, 16 Dec 2008 14:51:48 -0500 Received: from [199.232.76.173] (port=36818 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LCfxI-0006kr-6H for qemu-devel@nongnu.org; Tue, 16 Dec 2008 14:51:44 -0500 Received: from mx20.gnu.org ([199.232.41.8]:28963) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LCfxH-0006wA-Qx for qemu-devel@nongnu.org; Tue, 16 Dec 2008 14:51:43 -0500 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LCfxG-0001tw-OQ for qemu-devel@nongnu.org; Tue, 16 Dec 2008 14:51:43 -0500 Date: Tue, 16 Dec 2008 11:51:35 -0800 From: Nathan Froyd Subject: Re: [Qemu-devel] [PATCH 01/42] target-ppc: add Altivec logical operations. Message-ID: <20081216195135.GC24654@codesourcery.com> References: <1229307315-16807-1-git-send-email-froydnj@codesourcery.com> <1229307315-16807-2-git-send-email-froydnj@codesourcery.com> <20081215221152.GE8523@volta.aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20081215221152.GE8523@volta.aurel32.net> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Mon, Dec 15, 2008 at 11:11:52PM +0100, Aurelien Jarno wrote: > On Sun, Dec 14, 2008 at 06:14:34PM -0800, Nathan Froyd wrote: > > +GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 1028); > > +GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 1092); > > +GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 1156); > > +GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 1220); > > +GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 1284); > > I know those decimal value comes from the PowerPC manual, but the whole > QEMU code uses hexadecimal values instead. Also it is usually passed > directly as opc2 and opc3 values. I guess it is better to continue like > that for consistencies. > > Otherwise the patch looks good, I'll apply it when that is fixed. Updated patch below. I suppose this means redoing a good chunk of the remainder of the patch series, since the convenience macros use the XO field approach instead of opc2/opc3, eh? -Nathan Signed-off-by: Nathan Froyd --- Use opc2/opc3 instead of one big xo field. Do this consistency with the rest of translate.c --- target-ppc/translate.c | 18 ++++++++++++++++++ 1 files changed, 18 insertions(+), 0 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 4c4f9ef..0d1fd57 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -6109,6 +6109,24 @@ GEN_VR_STX(svx, 0x07, 0x07); /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ GEN_VR_STX(svxl, 0x07, 0x0F); +/* Logical operations */ +#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ +GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \ +{ \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \ + tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \ +} + +GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16); +GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17); +GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18); +GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19); +GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20); + /*** SPE extension ***/ /* Register moves */ -- 1.6.0.5