From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LDRkC-0004AJ-Ox for qemu-devel@nongnu.org; Thu, 18 Dec 2008 17:53:24 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LDRkB-00049k-Ti for qemu-devel@nongnu.org; Thu, 18 Dec 2008 17:53:24 -0500 Received: from [199.232.76.173] (port=41245 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LDRkB-00049f-QF for qemu-devel@nongnu.org; Thu, 18 Dec 2008 17:53:23 -0500 Received: from hall.aurel32.net ([88.191.82.174]:58145) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LDRkB-0000Qo-Ax for qemu-devel@nongnu.org; Thu, 18 Dec 2008 17:53:23 -0500 Date: Thu, 18 Dec 2008 23:53:20 +0100 From: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH] QEMU: Mask writes to RO bits in the status reg of PCI config space Message-ID: <20081218225320.GF12048@volta.aurel32.net> References: <1229442074-15153-1-git-send-email-amit.shah@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1229442074-15153-1-git-send-email-amit.shah@redhat.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Amit Shah On Tue, Dec 16, 2008 at 03:41:13PM +0000, Amit Shah wrote: > The Status register in the PCI config space has some read-only bits. > Any writes to those bits should be masked out. > > Signed-off-by: Amit Shah Thanks applied. > --- > qemu/hw/pci.c | 11 +++++++++++ > qemu/hw/pci.h | 15 +++++++++++++++ > 2 files changed, 26 insertions(+), 0 deletions(-) > > diff --git a/qemu/hw/pci.c b/qemu/hw/pci.c > index c93758d..f07892e 100644 > --- a/qemu/hw/pci.c > +++ b/qemu/hw/pci.c > @@ -416,6 +416,7 @@ void pci_default_write_config(PCIDevice *d, > case 0x0b: > case 0x0e: > case 0x10 ... 0x27: /* base */ > + case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */ > case 0x30 ... 0x33: /* rom */ > case 0x3d: > can_write = 0; > @@ -437,6 +438,7 @@ void pci_default_write_config(PCIDevice *d, > case 0x0a: > case 0x0b: > case 0x0e: > + case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */ > case 0x38 ... 0x3b: /* rom */ > case 0x3d: > can_write = 0; > @@ -448,6 +450,15 @@ void pci_default_write_config(PCIDevice *d, > break; > } > if (can_write) { > + /* Mask out writes to reserved bits in registers */ > + switch (addr) { > + case 0x06: > + val &= ~PCI_STATUS_RESERVED_MASK_LO; > + break; > + case 0x07: > + val &= ~PCI_STATUS_RESERVED_MASK_HI; > + break; > + } > d->config[addr] = val; > } > if (++addr > 0xff) > diff --git a/qemu/hw/pci.h b/qemu/hw/pci.h > index e11fbbf..d25b0ca 100644 > --- a/qemu/hw/pci.h > +++ b/qemu/hw/pci.h > @@ -46,6 +46,21 @@ typedef struct PCIIORegion { > #define PCI_MIN_GNT 0x3e /* 8 bits */ > #define PCI_MAX_LAT 0x3f /* 8 bits */ > > +/* Bits in the PCI Status Register (PCI 2.3 spec) */ > +#define PCI_STATUS_RESERVED1 0x007 > +#define PCI_STATUS_INT_STATUS 0x008 > +#define PCI_STATUS_CAPABILITIES 0x010 > +#define PCI_STATUS_66MHZ 0x020 > +#define PCI_STATUS_RESERVED2 0x040 > +#define PCI_STATUS_FAST_BACK 0x080 > +#define PCI_STATUS_DEVSEL 0x600 > + > +#define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \ > + PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \ > + PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK) > + > +#define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8) > + > struct PCIDevice { > /* PCI config space */ > uint8_t config[256]; > -- > 1.5.6.3 > > > > -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net