From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LKaqq-0002un-Gu for qemu-devel@nongnu.org; Wed, 07 Jan 2009 11:01:48 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LKaqn-0002uW-Q9 for qemu-devel@nongnu.org; Wed, 07 Jan 2009 11:01:47 -0500 Received: from [199.232.76.173] (port=42362 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LKaqn-0002uO-Mi for qemu-devel@nongnu.org; Wed, 07 Jan 2009 11:01:45 -0500 Received: from mx2.redhat.com ([66.187.237.31]:42431) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LKaqn-0002G4-4e for qemu-devel@nongnu.org; Wed, 07 Jan 2009 11:01:45 -0500 Received: from int-mx2.corp.redhat.com (int-mx2.corp.redhat.com [172.16.27.26]) by mx2.redhat.com (8.13.8/8.13.8) with ESMTP id n07G1iSl021054 for ; Wed, 7 Jan 2009 11:01:44 -0500 Date: Wed, 7 Jan 2009 18:02:55 +0200 From: Gleb Natapov Subject: Re: [Qemu-devel] [PATCH] mark nic as trusted Message-ID: <20090107160255.GG3267@redhat.com> References: <20090107142626.GE3267@redhat.com> <1231340671.5050.69.camel@localhost.localdomain> <20090107151912.GF3267@redhat.com> <1231342892.5050.70.camel@localhost.localdomain> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1231342892.5050.70.camel@localhost.localdomain> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Mark McLoughlin Cc: qemu-devel@nongnu.org On Wed, Jan 07, 2009 at 03:41:32PM +0000, Mark McLoughlin wrote: > On Wed, 2009-01-07 at 17:19 +0200, Gleb Natapov wrote: > > > > > + if (nd->secure_cookie[0]) > > > > + pci_add_capability(&n->vdev.pci_dev, 0x0f, 0xf0, nd->secure_cookie, 14); > > > > > > How was the Capability ID 0x0f chosen? It it unallocated by the PCI SIG > > > allocated it or ...? I see it's not defined in the kernel sources: > > > > > > #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */ > > > #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ > > > > > It is "secure device capability", so I used it based on the name. > > Ah, I see this in pciutils now: > > #define PCI_CAP_ID_SECURE 0x0F /* Secure device (?) */ > > Where is the capability format published? I can't seem to find any > specification for it ... > Me too. The only thing I found is that AMD barcelona chipset uses it. Look at page 260 of this doc for details how: http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116_PUB_BKDG-3-18_11-13-08.pdf I just hijacked the capability for our needs :) -- Gleb.