Re: [Qemu-devel] Qemu as a System Simulator

[Vince Weaver <vince@csl.cornell.edu>]

On Tue, 6 Jan 2009, Andrea Pellegrini wrote:

> I saw that many cycle accurate simulators are based on Qemu and I was 
> wondering if anyone has experience and thinks that is possible to modify Qemu 
> to support multiple interconnect (such as bus, mesh, NoC).

It's true that some simulation methodologies use Qemu for functional 
(correctness) simulation.  This is only a small part of a fully functional 
"cycle-accurate" simulator.  See the
    FPGA-Accelerated Simulation Technologies (FAST) work by
    Derek Chiou's group:
        http://users.ece.utexas.edu/~derek/FAST.html
    (I doubt you'll ever see any of their Qemu-related code released)


You can also use Qemu to generate traces for use in simulation.
In some cases, especially on RISC architectures like MIPS, you can
estimate CPI and similar metrics and get results using Qemu
that are similar to those generated by "cycle-accurate" simulators
like SESC.  See my paper here for more info on that:
    http://www.csl.cornell.edu/~vince/papers/wddd08/index.html


What you describe though would involve adding a lot of extra code to Qemu.
Qemu is set up for fast emulation of binaries, not for architectural 
research.  There isn't any built in cache or cache-coherence simulation, 
let alone any sort of idea of inter-chip interconnects.


So to answer your question, I do think it is possible to use Qemu in the 
way you describe.  Unfortunately I don't think it's practical or likely to 
happen any time soon.

Vince