From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LKh26-0003f2-Qt for qemu-devel@nongnu.org; Wed, 07 Jan 2009 17:37:50 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LKh25-0003eq-Hd for qemu-devel@nongnu.org; Wed, 07 Jan 2009 17:37:50 -0500 Received: from [199.232.76.173] (port=49509 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LKh25-0003en-E7 for qemu-devel@nongnu.org; Wed, 07 Jan 2009 17:37:49 -0500 Received: from csl.cornell.edu ([128.84.224.10]:1768 helo=vlsi.csl.cornell.edu) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LKh25-0002Qa-0v for qemu-devel@nongnu.org; Wed, 07 Jan 2009 17:37:49 -0500 Received: from stanley.csl.cornell.edu (stanley.csl.cornell.edu [128.84.224.15]) by vlsi.csl.cornell.edu (8.13.4/8.13.4) with ESMTP id n07MbcjQ067028 for ; Wed, 7 Jan 2009 17:37:43 -0500 (EST) Date: Wed, 7 Jan 2009 17:37:38 -0500 (EST) From: Vince Weaver Subject: Re: [Qemu-devel] Qemu as a System Simulator In-Reply-To: <4963B669.2040602@umich.edu> Message-ID: <20090107172617.E43342@stanley.csl.cornell.edu> References: <4963B669.2040602@umich.edu> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Tue, 6 Jan 2009, Andrea Pellegrini wrote: > I saw that many cycle accurate simulators are based on Qemu and I was > wondering if anyone has experience and thinks that is possible to modify Qemu > to support multiple interconnect (such as bus, mesh, NoC). It's true that some simulation methodologies use Qemu for functional (correctness) simulation. This is only a small part of a fully functional "cycle-accurate" simulator. See the FPGA-Accelerated Simulation Technologies (FAST) work by Derek Chiou's group: http://users.ece.utexas.edu/~derek/FAST.html (I doubt you'll ever see any of their Qemu-related code released) You can also use Qemu to generate traces for use in simulation. In some cases, especially on RISC architectures like MIPS, you can estimate CPI and similar metrics and get results using Qemu that are similar to those generated by "cycle-accurate" simulators like SESC. See my paper here for more info on that: http://www.csl.cornell.edu/~vince/papers/wddd08/index.html What you describe though would involve adding a lot of extra code to Qemu. Qemu is set up for fast emulation of binaries, not for architectural research. There isn't any built in cache or cache-coherence simulation, let alone any sort of idea of inter-chip interconnects. So to answer your question, I do think it is possible to use Qemu in the way you describe. Unfortunately I don't think it's practical or likely to happen any time soon. Vince