From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LKfuC-0000fm-Um for qemu-devel@nongnu.org; Wed, 07 Jan 2009 16:25:36 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LKfuA-0000fW-E2 for qemu-devel@nongnu.org; Wed, 07 Jan 2009 16:25:35 -0500 Received: from [199.232.76.173] (port=43634 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LKfuA-0000fT-An for qemu-devel@nongnu.org; Wed, 07 Jan 2009 16:25:34 -0500 Received: from mx20.gnu.org ([199.232.41.8]:30184) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LKfuA-00041z-0T for qemu-devel@nongnu.org; Wed, 07 Jan 2009 16:25:34 -0500 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LKfu9-0006xC-1V for qemu-devel@nongnu.org; Wed, 07 Jan 2009 16:25:33 -0500 Date: Wed, 7 Jan 2009 13:25:32 -0800 From: Nathan Froyd Subject: Re: [Qemu-devel] [PATCH 23/40] Add vspltis{b,h,w} instructions. Message-ID: <20090107212532.GF28711@codesourcery.com> References: <1230693022-18380-1-git-send-email-froydnj@codesourcery.com> <1230693022-18380-24-git-send-email-froydnj@codesourcery.com> <20090103214354.GD18974@volta.aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090103214354.GD18974@volta.aurel32.net> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Sat, Jan 03, 2009 at 10:43:54PM +0100, Aurelien Jarno wrote: > On Tue, Dec 30, 2008 at 07:10:05PM -0800, Nathan Froyd wrote: > > +#define VSPLTI(suffix, element, splat_type) \ > > + void helper_vspltis##suffix (ppc_avr_t *r, uint32_t splat) \ > > + { \ > > + splat_type x = (splat_type)splat; \ > > + int i; \ > > + /* 5-bit sign extension. */ \ > > + if (x & 0x10) \ > > + x -= 0x20; \ > > I don't really like this way of doing a sign extension. I would prefer > to avoid a test and do something like: > splat_type x = (int8_t)(splat << 3) >> 3; Done thusly. -Nathan Use more obvious sequence for 5-bit sign extension. Signed-off-by: Nathan Froyd --- target-ppc/helper.h | 3 +++ target-ppc/op_helper.c | 14 ++++++++++++++ target-ppc/translate.c | 20 ++++++++++++++++++++ 3 files changed, 37 insertions(+), 0 deletions(-) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index e15d6b0..755bfba 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -188,6 +188,9 @@ DEF_HELPER_3(vrlw, void, avr, avr, avr) DEF_HELPER_3(vsl, void, avr, avr, avr) DEF_HELPER_3(vsr, void, avr, avr, avr) DEF_HELPER_4(vsldoi, void, avr, avr, avr, i32) +DEF_HELPER_2(vspltisb, void, avr, i32) +DEF_HELPER_2(vspltish, void, avr, i32) +DEF_HELPER_2(vspltisw, void, avr, i32) DEF_HELPER_3(vspltb, void, avr, avr, i32) DEF_HELPER_3(vsplth, void, avr, avr, i32) DEF_HELPER_3(vspltw, void, avr, avr, i32) diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c index 81abd63..dc8ddfe 100644 --- a/target-ppc/op_helper.c +++ b/target-ppc/op_helper.c @@ -2609,6 +2609,20 @@ VSPLT(w, u32) #undef SPLAT_ELEMENT #undef _SPLAT_MASKED +#define VSPLTI(suffix, element, splat_type) \ + void helper_vspltis##suffix (ppc_avr_t *r, uint32_t splat) \ + { \ + splat_type x = (int8_t)(splat << 3) >> 3; \ + int i; \ + for (i = 0; i < ARRAY_SIZE(r->element); i++) { \ + r->element[i] = x; \ + } \ + } +VSPLTI(b, s8, int8_t) +VSPLTI(h, s16, int16_t) +VSPLTI(w, s32, int32_t) +#undef VSPLTI + #define VSR(suffix, element) \ void helper_vsr##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ { \ diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 65a80f2..6bb81d2 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -6404,6 +6404,26 @@ GEN_VXRFORM(vcmpgtub, 3, 8) GEN_VXRFORM(vcmpgtuh, 3, 9) GEN_VXRFORM(vcmpgtuw, 3, 10) +#define GEN_VXFORM_SIMM(name, opc2, opc3) \ + GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \ + { \ + TCGv_ptr rd; \ + TCGv_i32 simm; \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + simm = tcg_const_i32(SIMM5(ctx->opcode)); \ + rd = gen_avr_ptr(rD(ctx->opcode)); \ + gen_helper_##name (rd, simm); \ + tcg_temp_free_i32(simm); \ + tcg_temp_free_ptr(rd); \ + } + +GEN_VXFORM_SIMM(vspltisb, 6, 12); +GEN_VXFORM_SIMM(vspltish, 6, 13); +GEN_VXFORM_SIMM(vspltisw, 6, 14); + #define GEN_VXFORM_NOA(name, opc2, opc3) \ GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \ { \ -- 1.6.0.5