From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LKsCj-0006Ux-0R for qemu-devel@nongnu.org; Thu, 08 Jan 2009 05:33:33 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LKsCg-0006Tb-De for qemu-devel@nongnu.org; Thu, 08 Jan 2009 05:33:31 -0500 Received: from [199.232.76.173] (port=59479 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LKsCg-0006TO-4D for qemu-devel@nongnu.org; Thu, 08 Jan 2009 05:33:30 -0500 Received: from bart.se.axis.com ([195.60.68.10]:46064) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LKsCf-0005h2-Ov for qemu-devel@nongnu.org; Thu, 08 Jan 2009 05:33:29 -0500 Received: from bart.se.axis.com (bart.se.axis.com [127.0.0.1]) by bart.se.axis.com (Postfix) with ESMTP id 1A8CC64115 for ; Thu, 8 Jan 2009 11:33:29 +0100 (CET) Received: from axis.com (edgar.se.axis.com [10.93.151.1]) by bart.se.axis.com (Postfix) with ESMTP id F1C8564106 for ; Thu, 8 Jan 2009 11:33:28 +0100 (CET) Date: Thu, 8 Jan 2009 11:33:29 +0100 From: "Edgar E. Iglesias" Subject: Re: [Qemu-devel] [PATCH]: add leon target Message-ID: <20090108103328.GC26971@edgar.se.axis.com> References: <20090107102439.GA15209@ulanbator.act-europe.fr> <20090108100156.GB26971@edgar.se.axis.com> <7B084501-75D2-4E83-AA6B-EC8FD8B945A4@adacore.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <7B084501-75D2-4E83-AA6B-EC8FD8B945A4@adacore.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Tristan Gingold Cc: qemu-devel@nongnu.org On Thu, Jan 08, 2009 at 11:09:45AM +0100, Tristan Gingold wrote: >>> > > Hi, > > >>> I have the same feeling too. I am ready to improve the code but I need a >>> few advices. >>> As currently implemented CPU emulation know about interrupt controller. >>> Wether interrupt controller >>> belongs to CPU or to the board is an open question :-) >>> Do you simply prefer to have hooks in CPUSPARCState ? >> >> From my experience, interrupt controllers are usually not considered to >> be part of the CPU. > > (What about LAPIC/LSAPIC ?) There are ofcourse exceptions :) > >> Regarding the leon interrupt controller, I had a quick look at the vhdl >> and >> AFAICT there is no need for any special tricks in the sparc cpu model. >> What you need is to handle accesses to the interrupt clear register, in >> your >> code you seem to call it ITC and your io_writel does not handle it. >> This is the place to hook in calls to mask off bits from the pending >> interrupt reg. >> >> Your leon software should be writing to this register when acking >> interrupts. > > No. You have missed (p19): > > When the IU acknowledges the interrupt, the corresponding pending bit will > automatically be cleared. > > This is the only reason why the CPU must inform the interrupt controller. > Not sure what docs you are refering to, but I had a second look at the vhd and you seem to be correct. Odd... Best regards