From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LNwPH-0003kO-Mt for qemu-devel@nongnu.org; Fri, 16 Jan 2009 16:39:11 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LNwPH-0003jP-4Y for qemu-devel@nongnu.org; Fri, 16 Jan 2009 16:39:11 -0500 Received: from [199.232.76.173] (port=47048 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LNwPG-0003iu-In for qemu-devel@nongnu.org; Fri, 16 Jan 2009 16:39:10 -0500 Received: from hall.aurel32.net ([88.191.82.174]:36640) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LNwPF-0000Bp-Ud for qemu-devel@nongnu.org; Fri, 16 Jan 2009 16:39:10 -0500 Date: Fri, 16 Jan 2009 22:39:06 +0100 From: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH] hpet config mask fix Message-ID: <20090116213906.GC22128@volta.aurel32.net> References: <496DFA90.8050100@us.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <496DFA90.8050100@us.ibm.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: kvm On Wed, Jan 14, 2009 at 09:45:36AM -0500, Beth Kon wrote: > I discovered a bug in the hpet code that caused Windows to boot without > hpet. The config mask I was using was preventing the guest from placing > the hpet into 32 bit mode. > Thanks, applied. > diff --git a/qemu/hw/hpet.c b/qemu/hw/hpet.c > index 5c1aca2..7df2d05 100644 > --- a/qemu/hw/hpet.c > +++ b/qemu/hw/hpet.c > @@ -388,7 +388,8 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr, > switch ((addr - 0x100) % 0x20) { > case HPET_TN_CFG: > dprintf("qemu: hpet_ram_writel HPET_TN_CFG\n"); > - timer->config = hpet_fixup_reg(new_val, old_val, 0x3e4e); > + timer->config = hpet_fixup_reg(new_val, old_val, > + HPET_TN_CFG_WRITE_MASK); > if (new_val & HPET_TN_32BIT) { > timer->cmp = (uint32_t)timer->cmp; > timer->period = (uint32_t)timer->period; > @@ -456,7 +457,8 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr, > case HPET_ID: > return; > case HPET_CFG: > - s->config = hpet_fixup_reg(new_val, old_val, 0x3); > + s->config = hpet_fixup_reg(new_val, old_val, > + HPET_CFG_WRITE_MASK); > if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) { > /* Enable main counter and interrupt generation. */ > s->hpet_offset = ticks_to_ns(s->hpet_counter) > diff --git a/qemu/hw/hpet_emul.h b/qemu/hw/hpet_emul.h > index fbe7a44..60893b6 100644 > --- a/qemu/hw/hpet_emul.h > +++ b/qemu/hw/hpet_emul.h > @@ -36,6 +36,7 @@ > #define HPET_TN_CFG 0x000 > #define HPET_TN_CMP 0x008 > #define HPET_TN_ROUTE 0x010 > +#define HPET_CFG_WRITE_MASK 0x3 > > > #define HPET_TN_ENABLE 0x004 > @@ -45,6 +46,7 @@ > #define HPET_TN_SETVAL 0x040 > #define HPET_TN_32BIT 0x100 > #define HPET_TN_INT_ROUTE_MASK 0x3e00 > +#define HPET_TN_CFG_WRITE_MASK 0x3f4e > #define HPET_TN_INT_ROUTE_SHIFT 9 > #define HPET_TN_INT_ROUTE_CAP_SHIFT 32 > #define HPET_TN_CFG_BITS_READONLY_OR_RESERVED 0xffff80b1U -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net