From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LPAVi-0004IX-Cy for qemu-devel@nongnu.org; Tue, 20 Jan 2009 01:54:54 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LPAVf-0004EH-5w for qemu-devel@nongnu.org; Tue, 20 Jan 2009 01:54:51 -0500 Received: from [199.232.76.173] (port=37825 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LPAVf-0004E9-0S for qemu-devel@nongnu.org; Tue, 20 Jan 2009 01:54:51 -0500 Received: from cdptpa-omtalb.mail.rr.com ([75.180.132.122]:62427) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LPAVe-0001IN-I8 for qemu-devel@nongnu.org; Tue, 20 Jan 2009 01:54:50 -0500 Received: from localhost.localdomain ([76.88.95.122]) by cdptpa-omta04.mail.rr.com with ESMTP id <20090120065449.QJBU2046.cdptpa-omta04.mail.rr.com@localhost.localdomain> for ; Tue, 20 Jan 2009 06:54:49 +0000 Date: Mon, 19 Jan 2009 22:54:43 -0800 From: Andrew May Message-ID: <20090119225443.0b65f8b1@acmay.homeip.net> In-Reply-To: <20090117002513.2e2a5aed@acmay.homeip.net> References: <20090117002513.2e2a5aed@acmay.homeip.net> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="MP_/GfYTg1kYkwBAcQfa26pqt/v" Subject: [Qemu-devel] Re: 4xx booting into Linux userspace Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org --MP_/GfYTg1kYkwBAcQfa26pqt/v Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Content-Disposition: inline On Sat, 17 Jan 2009 00:25:13 -0800 Andrew May wrote: > I finally got a 405 linux kernel booted into userspace. > The op_helper change is pretty straight forward, where the "tlb->attr" > values should have been set from the tlbwe_lo function instead of the > high function. > I am not sure that the tlb->attr bits completely line up with the > tlbwe_lo bits, since I don't know how else they are used besides the > zone bits. > > For the helper.c I am not sure on the best way to deal with things. > The first change should be ok, where the zone mapping was just off. > But the other part where the 405 SPR doesn't seem to match up with > SPR's used in the core TLB lookup code. Just after I sent this I realized I didn't include the older patches I had posted to the list on getting the 4xx stuff going. And then when I tried to sync to the lastest I hit a snag with the display changes. I feel pretty good about all the op_helper.c fixes. 1. Don't abort on Little endian pages, if they aren't valid. 2. Fix tlb->attr to get setting from lo reg instead of the high one. 3. Allow 4xx_tlbwe_lo, writes to leave the "tlb->prot valid" bit set, and invalid pages to get the updates. I don't know the best way to handle the spr SPR_DAR vs SPR_40x_DEAR difference in helper.c So if anyone knows the best way to address this, please let me know. And I am not on the list so, please CC me. Thanks. --MP_/GfYTg1kYkwBAcQfa26pqt/v Content-Type: text/x-patch; name=4xx_working.patch Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename=4xx_working.patch diff --git a/trunk/target-ppc/helper.c b/trunk/target-ppc/helper.c index 2bf7650..df37152 100644 --- a/trunk/target-ppc/helper.c +++ b/trunk/target-ppc/helper.c @@ -1141,7 +1141,7 @@ static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx, env->spr[SPR_40x_PID], 0, i) < 0) continue; zsel = (tlb->attr >> 4) & 0xF; - zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3; + zpr = (env->spr[SPR_40x_ZPR] >> (30 - (2 * zsel))) & 0x3; LOG_SWTLB("%s: TLB %d zsel %d zpr %d rw %d attr %08x\n", __func__, i, zsel, zpr, rw, tlb->attr); /* Check execute enable bit */ @@ -2089,6 +2089,9 @@ static always_inline void powerpc_excp (CPUState *env, new_msr &= ~((target_ulong)1 << MSR_RI); if (lpes1 == 0) new_msr |= (target_ulong)MSR_HVB; + /*Not sure why this isn't the same */ + env->spr[SPR_40x_DEAR] = env->spr[SPR_DAR]; + env->spr[SPR_40x_ESR] = 0x00800000; goto store_next; case POWERPC_EXCP_ISI: /* Instruction storage exception */ LOG_EXCP("ISI exception: msr=" ADDRX ", nip=" ADDRX "\n", diff --git a/trunk/target-ppc/op_helper.c b/trunk/target-ppc/op_helper.c index d531dd8..e165424 100644 --- a/trunk/target-ppc/op_helper.c +++ b/trunk/target-ppc/op_helper.c @@ -3737,12 +3737,11 @@ void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val) tlb->prot |= PAGE_VALID; else tlb->prot &= ~PAGE_VALID; - if (val & 0x20) { + if (val & 0x40 && val & 0x20) { /* XXX: TO BE FIXED */ cpu_abort(env, "Little-endian TLB entries are not supported by now\n"); } tlb->PID = env->spr[SPR_40x_PID]; /* PID */ - tlb->attr = val & 0xFF; LOG_SWTLB("%s: set up TLB %d RPN " PADDRX " EPN " ADDRX " size " ADDRX " prot %c%c%c%c PID %d\n", __func__, (int)entry, tlb->RPN, tlb->EPN, tlb->size, @@ -3768,11 +3767,21 @@ void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val) entry &= 0x3F; tlb = &env->tlb[entry].tlbe; tlb->RPN = val & 0xFFFFFC00; - tlb->prot = PAGE_READ; + tlb->attr = val & 0xFF; + tlb->prot &= ~(PAGE_EXEC | PAGE_WRITE); + tlb->prot |= PAGE_READ; if (val & 0x200) tlb->prot |= PAGE_EXEC; if (val & 0x100) tlb->prot |= PAGE_WRITE; + + /* If the page is valid flush it for the prot change */ + if (tlb->prot & PAGE_VALID) { + target_ulong page, end; + end = tlb->EPN + tlb->size; + for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) + tlb_flush_page(env, page); + } LOG_SWTLB("%s: set up TLB %d RPN " PADDRX " EPN " ADDRX " size " ADDRX " prot %c%c%c%c PID %d\n", __func__, (int)entry, tlb->RPN, tlb->EPN, tlb->size, --MP_/GfYTg1kYkwBAcQfa26pqt/v--