From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LPbbT-00019U-2p for qemu-devel@nongnu.org; Wed, 21 Jan 2009 06:50:39 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LPbbQ-00018p-6N for qemu-devel@nongnu.org; Wed, 21 Jan 2009 06:50:38 -0500 Received: from [199.232.76.173] (port=37529 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LPbbQ-00018k-1F for qemu-devel@nongnu.org; Wed, 21 Jan 2009 06:50:36 -0500 Received: from mail-qy0-f20.google.com ([209.85.221.20]:60662) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LPbbP-0007Sa-IC for qemu-devel@nongnu.org; Wed, 21 Jan 2009 06:50:35 -0500 Received: by qyk13 with SMTP id 13so5494003qyk.10 for ; Wed, 21 Jan 2009 03:50:34 -0800 (PST) Date: Wed, 21 Jan 2009 06:52:01 -0500 From: Mike Day Message-ID: <20090121115201.GA12504@silverwood.ncultra.org> References: <1232308399-21679-1-git-send-email-avi@redhat.com> <1232308399-21679-2-git-send-email-avi@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1232308399-21679-2-git-send-email-avi@redhat.com> Subject: [Qemu-devel] Re: Add target memory mapping API Reply-To: ncmike@ncultra.org, qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On 18/01/09 21:53 +0200, Avi Kivity wrote: > Devices accessing large amounts of memory (as with DMA) will wish to obtain > a pointer to guest memory rather than access it indirectly via > cpu_physical_memory_rw(). Add a new API to convert target addresses to > host pointers. > > In case the target address does not correspond to RAM, a bounce buffer is > allocated. To prevent the guest from causing the host to allocate unbounded > amounts of bounce buffer, this memory is limited (currently to one page). > > Signed-off-by: Avi Kivity > --- > cpu-all.h | 5 +++ > exec.c | 93 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 98 insertions(+), 0 deletions(-) > > diff --git a/cpu-all.h b/cpu-all.h > index ee0a6e3..3439999 100644 > --- a/cpu-all.h > +++ b/cpu-all.h > @@ -923,6 +923,11 @@ static inline void cpu_physical_memory_write(target_phys_addr_t addr, > { > cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1); > } > +void *cpu_physical_memory_map(target_phys_addr_t addr, > + target_phys_addr_t *plen, > + int is_write); > +void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len, > + int is_write); > uint32_t ldub_phys(target_phys_addr_t addr); > uint32_t lduw_phys(target_phys_addr_t addr); > uint32_t ldl_phys(target_phys_addr_t addr); > diff --git a/exec.c b/exec.c > index faa6333..7162271 100644 > --- a/exec.c > +++ b/exec.c > @@ -3045,6 +3045,99 @@ void cpu_physical_memory_write_rom(target_phys_addr_t addr, > } > } > > +typedef struct { > + void *buffer; > + target_phys_addr_t addr; > + target_phys_addr_t len; > +} BounceBuffer; > + > +static BounceBuffer bounce; Should there be one bounce buffer for each vcpu? Eventually the device model lock will be refactored to allow more parallelism, right? Mike -- Mike Day http://www.ncultra.org AIM: ncmikeday | Yahoo IM: ultra.runner PGP key: http://www.ncultra.org/ncmike/pubkey.asc