From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LQn5a-0003mK-Ck for qemu-devel@nongnu.org; Sat, 24 Jan 2009 13:18:38 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LQn5a-0003m4-01 for qemu-devel@nongnu.org; Sat, 24 Jan 2009 13:18:38 -0500 Received: from [199.232.76.173] (port=33349 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LQn5Z-0003lv-I5 for qemu-devel@nongnu.org; Sat, 24 Jan 2009 13:18:37 -0500 Received: from hall.aurel32.net ([88.191.82.174]:56198) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LQn5Z-0001e9-1S for qemu-devel@nongnu.org; Sat, 24 Jan 2009 13:18:37 -0500 Received: from volta.aurel32.net ([2002:52e8:2fb:1:21e:8cff:feb0:693b]) by hall.aurel32.net with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1LQn5X-00087p-Eb for qemu-devel@nongnu.org; Sat, 24 Jan 2009 19:18:35 +0100 Received: from aurel32 by volta.aurel32.net with local (Exim 4.69) (envelope-from ) id 1LQn5W-0003qK-Qt for qemu-devel@nongnu.org; Sat, 24 Jan 2009 19:18:34 +0100 Date: Sat, 24 Jan 2009 19:18:34 +0100 From: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH] sh4: sh_pci. Register resouces both at A7 and P4. Message-ID: <20090124181834.GD16336@volta.aurel32.net> References: <200812141808.mBEI8Y21019042@smtp11.dti.ne.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <200812141808.mBEI8Y21019042@smtp11.dti.ne.jp> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Mon, Dec 15, 2008 at 03:08:34AM +0900, takasi-y@ops.dti.ne.jp wrote: > Add resource registration both for P4 and A7. > This is needed because of #5935 SH4: Eliminate P4 to A7 mangling. > Additionally, {reg,iop,mem}base which is no longer used are removed. > > Signed-off-by: Takashi YOSHII > --- > hw/sh_pci.c | 17 +++++++---------- > 1 files changed, 7 insertions(+), 10 deletions(-) Thanks, applied. > diff --git a/hw/sh_pci.c b/hw/sh_pci.c > index 5524c59..9f89f2d 100644 > --- a/hw/sh_pci.c > +++ b/hw/sh_pci.c > @@ -29,9 +29,6 @@ > typedef struct { > PCIBus *bus; > PCIDevice *dev; > - uint32_t regbase; > - uint32_t iopbase; > - uint32_t membase; > uint32_t par; > uint32_t mbr; > uint32_t iobr; > @@ -181,15 +178,15 @@ PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, > > p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice), > -1, NULL, NULL); > - p->regbase = 0x1e200000; > - p->iopbase = 0x1e240000; > - p->membase = 0xfd000000; > reg = cpu_register_io_memory(0, sh_pci_reg.r, sh_pci_reg.w, p); > - mem = cpu_register_io_memory(0, sh_pci_mem.r, sh_pci_mem.w, p); > iop = cpu_register_io_memory(0, sh_pci_iop.r, sh_pci_iop.w, p); > - cpu_register_physical_memory(p->regbase, 0x224, reg); > - cpu_register_physical_memory(p->iopbase, 0x40000, iop); > - cpu_register_physical_memory(p->membase, 0x1000000, mem); > + mem = cpu_register_io_memory(0, sh_pci_mem.r, sh_pci_mem.w, p); > + cpu_register_physical_memory(0x1e200000, 0x224, reg); > + cpu_register_physical_memory(0x1e240000, 0x40000, iop); > + cpu_register_physical_memory(0x1d000000, 0x1000000, mem); > + cpu_register_physical_memory(0xfe200000, 0x224, reg); > + cpu_register_physical_memory(0xfe240000, 0x40000, iop); > + cpu_register_physical_memory(0xfd000000, 0x1000000, mem); > > p->dev->config[0x00] = 0x54; // HITACHI > p->dev->config[0x01] = 0x10; // > -- > 1.5.6.3 > > > /yoshii > > > -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net