From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LTgYJ-0002B9-Dc for qemu-devel@nongnu.org; Sun, 01 Feb 2009 12:56:15 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LTgYI-00029K-3j for qemu-devel@nongnu.org; Sun, 01 Feb 2009 12:56:15 -0500 Received: from [199.232.76.173] (port=35606 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LTgYI-000296-0L for qemu-devel@nongnu.org; Sun, 01 Feb 2009 12:56:14 -0500 Received: from mtaout03-winn.ispmail.ntl.com ([81.103.221.49]:56007) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LTgYH-0000kI-9H for qemu-devel@nongnu.org; Sun, 01 Feb 2009 12:56:13 -0500 Received: from aamtaout04-winn.ispmail.ntl.com ([81.103.221.35]) by mtaout03-winn.ispmail.ntl.com (InterMail vM.7.08.04.00 201-2186-134-20080326) with ESMTP id <20090201175612.ZQNA7670.mtaout03-winn.ispmail.ntl.com@aamtaout04-winn.ispmail.ntl.com> for ; Sun, 1 Feb 2009 17:56:12 +0000 Received: from miranda.arrow ([213.107.21.171]) by aamtaout04-winn.ispmail.ntl.com (InterMail vG.2.02.00.01 201-2161-120-102-20060912) with ESMTP id <20090201175611.NXLF22934.aamtaout04-winn.ispmail.ntl.com@miranda.arrow> for ; Sun, 1 Feb 2009 17:56:11 +0000 Received: from sdb by miranda.arrow with local (Exim 4.63) (envelope-from ) id 1LTgYD-0003jD-EG for qemu-devel@nongnu.org; Sun, 01 Feb 2009 17:56:09 +0000 Date: Sun, 1 Feb 2009 17:56:09 +0000 From: Stuart Brady Message-ID: <20090201175609.GA14322@miranda.arrow> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Subject: [Qemu-devel] [PATCH] Add and use #defines for PCI device classes Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This patch adds and uses #defines for PCI device classes and subclases, using a new pci_config_set_class() function, similar to the recently added pci_config_set_vendor_id() and pci_config_set_device_id(). Index: hw/virtio-balloon.c =================================================================== --- hw/virtio-balloon.c (revision 6490) +++ hw/virtio-balloon.c (working copy) @@ -176,7 +176,7 @@ void *virtio_balloon_init(PCIBus *bus) PCI_DEVICE_ID_VIRTIO_BALLOON, PCI_VENDOR_ID_REDHAT_QUMRANET, VIRTIO_ID_BALLOON, - 0x05, 0x00, 0x00, + PCI_CLASS_MEMORY_RAM, 0x00, 8, sizeof(VirtIOBalloon)); if (s == NULL) return NULL; Index: hw/cirrus_vga.c =================================================================== --- hw/cirrus_vga.c (revision 6490) +++ hw/cirrus_vga.c (working copy) @@ -3378,8 +3378,7 @@ void pci_cirrus_vga_init(PCIBus *bus, uint8_t *vga pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CIRRUS); pci_config_set_device_id(pci_conf, device_id); pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS; - pci_conf[0x0a] = PCI_CLASS_SUB_VGA; - pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY; + pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA); pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h; /* setup VGA */ Index: hw/usb-uhci.c =================================================================== --- hw/usb-uhci.c (revision 6490) +++ hw/usb-uhci.c (working copy) @@ -1084,8 +1084,7 @@ void usb_uhci_piix3_init(PCIBus *bus, int devfn) pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_2); pci_conf[0x08] = 0x01; // revision number pci_conf[0x09] = 0x00; - pci_conf[0x0a] = 0x03; - pci_conf[0x0b] = 0x0c; + pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB); pci_conf[0x0e] = 0x00; // header_type pci_conf[0x3d] = 4; // interrupt pin 3 pci_conf[0x60] = 0x10; // release number @@ -1119,8 +1118,7 @@ void usb_uhci_piix4_init(PCIBus *bus, int devfn) pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_2); pci_conf[0x08] = 0x01; // revision number pci_conf[0x09] = 0x00; - pci_conf[0x0a] = 0x03; - pci_conf[0x0b] = 0x0c; + pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB); pci_conf[0x0e] = 0x00; // header_type pci_conf[0x3d] = 4; // interrupt pin 3 pci_conf[0x60] = 0x10; // release number Index: hw/pcnet.c =================================================================== --- hw/pcnet.c (revision 6490) +++ hw/pcnet.c (working copy) @@ -2006,8 +2006,7 @@ void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int *(uint16_t *)&pci_conf[0x06] = cpu_to_le16(0x0280); pci_conf[0x08] = 0x10; pci_conf[0x09] = 0x00; - pci_conf[0x0a] = 0x00; // ethernet network controller - pci_conf[0x0b] = 0x02; + pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); pci_conf[0x0e] = 0x00; // header_type *(uint32_t *)&pci_conf[0x10] = cpu_to_le32(0x00000001); Index: hw/usb-ohci.c =================================================================== --- hw/usb-ohci.c (revision 6490) +++ hw/usb-ohci.c (working copy) @@ -1682,8 +1682,7 @@ void usb_ohci_init_pci(struct PCIBus *bus, int num pci_config_set_vendor_id(ohci->pci_dev.config, PCI_VENDOR_ID_APPLE); pci_config_set_device_id(ohci->pci_dev.config, 0x003f); // device_id ohci->pci_dev.config[0x09] = 0x10; /* OHCI */ - ohci->pci_dev.config[0x0a] = 0x3; - ohci->pci_dev.config[0x0b] = 0xc; + pci_config_set_class(ohci->pci_dev.config, PCI_CLASS_SERIAL_USB); ohci->pci_dev.config[0x3d] = 0x01; /* interrupt pin 1 */ usb_ohci_init(&ohci->state, num_ports, devfn, ohci->pci_dev.irq[0], Index: hw/acpi.c =================================================================== --- hw/acpi.c (revision 6490) +++ hw/acpi.c (working copy) @@ -509,8 +509,7 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uin pci_conf[0x07] = 0x02; pci_conf[0x08] = 0x03; // revision number pci_conf[0x09] = 0x00; - pci_conf[0x0a] = 0x80; // other bridge device - pci_conf[0x0b] = 0x06; // bridge device + pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER); pci_conf[0x0e] = 0x00; // header_type pci_conf[0x3d] = 0x01; // interrupt pin 1 Index: hw/apb_pci.c =================================================================== --- hw/apb_pci.c (revision 6490) +++ hw/apb_pci.c (working copy) @@ -260,8 +260,7 @@ PCIBus *pci_apb_init(target_phys_addr_t special_ba d->config[0x07] = 0x03; // status = medium devsel d->config[0x08] = 0x00; // revision d->config[0x09] = 0x00; // programming i/f - d->config[0x0A] = 0x00; // class_sub = pci host - d->config[0x0B] = 0x06; // class_base = PCI_bridge + pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); d->config[0x0D] = 0x10; // latency_timer d->config[0x0E] = 0x00; // header_type Index: hw/unin_pci.c =================================================================== --- hw/unin_pci.c (revision 6490) +++ hw/unin_pci.c (working copy) @@ -177,8 +177,7 @@ PCIBus *pci_pmac_init(qemu_irq *pic) pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE); pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI); d->config[0x08] = 0x00; // revision - d->config[0x0A] = 0x00; // class_sub = pci host - d->config[0x0B] = 0x06; // class_base = PCI_bridge + pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); d->config[0x0C] = 0x08; // cache_line_size d->config[0x0D] = 0x10; // latency_timer d->config[0x0E] = 0x00; // header_type @@ -191,8 +190,7 @@ PCIBus *pci_pmac_init(qemu_irq *pic) pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC); pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154); d->config[0x08] = 0x05; // revision - d->config[0x0A] = 0x04; // class_sub = pci2pci - d->config[0x0B] = 0x06; // class_base = PCI_bridge + pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI); d->config[0x0C] = 0x08; // cache_line_size d->config[0x0D] = 0x20; // latency_timer d->config[0x0E] = 0x01; // header_type @@ -228,8 +226,7 @@ PCIBus *pci_pmac_init(qemu_irq *pic) pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE); pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP); d->config[0x08] = 0x00; // revision - d->config[0x0A] = 0x00; // class_sub = pci host - d->config[0x0B] = 0x06; // class_base = PCI_bridge + pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); d->config[0x0C] = 0x08; // cache_line_size d->config[0x0D] = 0x10; // latency_timer d->config[0x0E] = 0x00; // header_type @@ -251,8 +248,7 @@ PCIBus *pci_pmac_init(qemu_irq *pic) pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE); pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI); d->config[0x08] = 0x00; // revision - d->config[0x0A] = 0x00; // class_sub = pci host - d->config[0x0B] = 0x06; // class_base = PCI_bridge + pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); d->config[0x0C] = 0x08; // cache_line_size d->config[0x0D] = 0x10; // latency_timer d->config[0x0E] = 0x00; // header_type Index: hw/vmware_vga.c =================================================================== --- hw/vmware_vga.c (revision 6490) +++ hw/vmware_vga.c (working copy) @@ -1204,8 +1204,6 @@ static void pci_vmsvga_map_mem(PCIDevice *pci_dev, iomemtype); } -#define PCI_CLASS_BASE_DISPLAY 0x03 -#define PCI_CLASS_SUB_VGA 0x00 #define PCI_CLASS_HEADERTYPE_00h 0x00 void pci_vmsvga_init(PCIBus *bus, uint8_t *vga_ram_base, @@ -1220,8 +1218,7 @@ void pci_vmsvga_init(PCIBus *bus, uint8_t *vga_ram pci_config_set_vendor_id(s->card.config, PCI_VENDOR_ID_VMWARE); pci_config_set_device_id(s->card.config, SVGA_PCI_DEVICE_ID); s->card.config[PCI_COMMAND] = 0x07; /* I/O + Memory */ - s->card.config[PCI_CLASS_DEVICE] = PCI_CLASS_SUB_VGA; - s->card.config[0x0b] = PCI_CLASS_BASE_DISPLAY; + pci_config_set_class(s->card.config, PCI_CLASS_DISPLAY_VGA); s->card.config[0x0c] = 0x08; /* Cache line size */ s->card.config[0x0d] = 0x40; /* Latency timer */ s->card.config[0x0e] = PCI_CLASS_HEADERTYPE_00h; Index: hw/grackle_pci.c =================================================================== --- hw/grackle_pci.c (revision 6490) +++ hw/grackle_pci.c (working copy) @@ -148,8 +148,7 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq * pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_MPC106); d->config[0x08] = 0x00; // revision d->config[0x09] = 0x01; - d->config[0x0a] = 0x00; // class_sub = host - d->config[0x0b] = 0x06; // class_base = PCI_bridge + pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); d->config[0x0e] = 0x00; // header_type #if 0 @@ -157,8 +156,7 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq * pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC); pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154); d->config[0x08] = 0x02; // revision - d->config[0x0a] = 0x04; // class_sub = pci2pci - d->config[0x0b] = 0x06; // class_base = PCI_bridge + pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI); d->config[0x0e] = 0x01; // header_type d->config[0x18] = 0x0; // primary_bus Index: hw/prep_pci.c =================================================================== --- hw/prep_pci.c (revision 6490) +++ hw/prep_pci.c (working copy) @@ -158,8 +158,7 @@ PCIBus *pci_prep_init(qemu_irq *pic) pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA); pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_RAVEN); d->config[0x08] = 0x00; // revision - d->config[0x0A] = 0x00; // class_sub = pci host - d->config[0x0B] = 0x06; // class_base = PCI_bridge + pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); d->config[0x0C] = 0x08; // cache_line_size d->config[0x0D] = 0x10; // latency_timer d->config[0x0E] = 0x00; // header_type Index: hw/ide.c =================================================================== --- hw/ide.c (revision 6490) +++ hw/ide.c (working copy) @@ -3353,8 +3353,7 @@ void pci_cmd646_ide_init(PCIBus *bus, BlockDriverS pci_conf[0x08] = 0x07; // IDE controller revision pci_conf[0x09] = 0x8f; - pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE - pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage + pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE); pci_conf[0x0e] = 0x00; // header_type pci_conf[0x51] = 0x04; // enable IDE0 @@ -3423,8 +3422,7 @@ void pci_piix3_ide_init(PCIBus *bus, BlockDriverSt pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_1); pci_conf[0x09] = 0x80; // legacy ATA mode - pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE - pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage + pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE); pci_conf[0x0e] = 0x00; // header_type qemu_register_reset(piix3_reset, d); @@ -3460,8 +3458,7 @@ void pci_piix4_ide_init(PCIBus *bus, BlockDriverSt pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB); pci_conf[0x09] = 0x80; // legacy ATA mode - pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE - pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage + pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE); pci_conf[0x0e] = 0x00; // header_type qemu_register_reset(piix3_reset, d); Index: hw/ac97.c =================================================================== --- hw/ac97.c (revision 6490) +++ hw/ac97.c (working copy) @@ -1347,8 +1347,7 @@ int ac97_init (PCIBus *bus, AudioState *audio) c[0x08] = 0x01; /* rid revision ro */ c[0x09] = 0x00; /* pi programming interface ro */ - c[0x0a] = 0x01; /* scc sub class code ro */ - c[0x0b] = 0x04; /* bcc base class code ro */ + pci_config_set_class(c, PCI_CLASS_MULTIMEDIA_AUDIO); /* ro */ c[0x0e] = 0x00; /* headtyp header type ro */ c[0x10] = 0x01; /* nabmar native audio mixer base Index: hw/openpic.c =================================================================== --- hw/openpic.c (revision 6490) +++ hw/openpic.c (working copy) @@ -1019,8 +1019,7 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_ind pci_conf = opp->pci_dev.config; pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM); pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_OPENPIC2); - pci_conf[0x0a] = 0x80; // PIC - pci_conf[0x0b] = 0x08; + pci_config_set_class(pci_conf, PCI_CLASS_SYSTEM_OTHER); // FIXME? pci_conf[0x0e] = 0x00; // header_type pci_conf[0x3d] = 0x00; // no interrupt pin Index: hw/pci.c =================================================================== --- hw/pci.c (revision 6490) +++ hw/pci.c (working copy) @@ -729,8 +729,7 @@ PCIBus *pci_bridge_init(PCIBus *bus, int devfn, ui s->dev.config[0x07] = 0x00; // status = fast devsel s->dev.config[0x08] = 0x00; // revision s->dev.config[0x09] = 0x00; // programming i/f - s->dev.config[0x0A] = 0x04; // class_sub = PCI to PCI bridge - s->dev.config[0x0B] = 0x06; // class_base = PCI_bridge + pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI); s->dev.config[0x0D] = 0x10; // latency_timer s->dev.config[0x0E] = 0x81; // header_type s->dev.config[0x1E] = 0xa0; // secondary status Index: hw/pci.h =================================================================== --- hw/pci.h (revision 6490) +++ hw/pci.h (working copy) @@ -8,6 +8,36 @@ extern target_phys_addr_t pci_mem_base; +/* Device classes and subclasses */ + +#define PCI_CLASS_STORAGE_SCSI 0x0100 +#define PCI_CLASS_STORAGE_IDE 0x0101 +#define PCI_CLASS_STORAGE_OTHER 0x0180 + +#define PCI_CLASS_NETWORK_ETHERNET 0x0200 + +#define PCI_CLASS_DISPLAY_VGA 0x0300 +#define PCI_CLASS_DISPLAY_OTHER 0x0380 + +#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 + +#define PCI_CLASS_MEMORY_RAM 0x0500 + +#define PCI_CLASS_SYSTEM_OTHER 0x0880 + +#define PCI_CLASS_SERIAL_USB 0x0c03 + +#define PCI_CLASS_BRIDGE_HOST 0x0600 +#define PCI_CLASS_BRIDGE_ISA 0x0601 +#define PCI_CLASS_BRIDGE_PCI 0x0604 +#define PCI_CLASS_BRIDGE_OTHER 0x0680 + +#define PCI_CLASS_PROCESSOR_CO 0x0b40 + +#define PCI_CLASS_OTHERS 0xff + +/* Vendors and devices. */ + #define PCI_VENDOR_ID_LSI_LOGIC 0x1000 #define PCI_DEVICE_ID_LSI_53C895A 0x0012 @@ -209,6 +239,12 @@ pci_config_set_device_id(uint8_t *pci_config, uint cpu_to_le16wu((uint16_t *)&pci_config[PCI_DEVICE_ID], val); } +static inline void +pci_config_set_class(uint8_t *pci_config, uint16_t val) +{ + cpu_to_le16wu((uint16_t *)&pci_config[PCI_CLASS_DEVICE], val); +} + /* lsi53c895a.c */ #define LSI_MAX_DEVS 7 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id); Index: hw/eepro100.c =================================================================== --- hw/eepro100.c (revision 6490) +++ hw/eepro100.c (working copy) @@ -433,8 +433,7 @@ static void pci_reset(EEPRO100State * s) PCI_CONFIG_8(PCI_REVISION_ID, 0x08); /* PCI Class Code */ PCI_CONFIG_8(0x09, 0x00); - PCI_CONFIG_8(PCI_SUBCLASS_CODE, 0x00); // ethernet network controller - PCI_CONFIG_8(PCI_CLASS_CODE, 0x02); // network controller + pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); /* PCI Cache Line Size */ /* check cache line size!!! */ //~ PCI_CONFIG_8(0x0c, 0x00); Index: hw/ne2000.c =================================================================== --- hw/ne2000.c (revision 6490) +++ hw/ne2000.c (working copy) @@ -792,8 +792,7 @@ void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int pci_conf = d->dev.config; pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK); pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_RTL8029); - pci_conf[0x0a] = 0x00; // ethernet network controller - pci_conf[0x0b] = 0x02; + pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); pci_conf[0x0e] = 0x00; // header_type pci_conf[0x3d] = 1; // interrupt pin 0 Index: hw/versatile_pci.c =================================================================== --- hw/versatile_pci.c (revision 6490) +++ hw/versatile_pci.c (working copy) @@ -133,8 +133,7 @@ PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int r d->config[0x07] = 0x02; d->config[0x08] = 0x00; // revision d->config[0x09] = 0x00; // programming i/f - d->config[0x0A] = 0x40; // class_sub = pci host - d->config[0x0B] = 0x0b; // class_base = PCI_bridge + pci_config_set_class(d->config, PCI_CLASS_PROCESSOR_CO); d->config[0x0D] = 0x10; // latency_timer return s; Index: hw/virtio-net.c =================================================================== --- hw/virtio-net.c (revision 6490) +++ hw/virtio-net.c (working copy) @@ -325,7 +325,7 @@ void virtio_net_init(PCIBus *bus, NICInfo *nd, int PCI_DEVICE_ID_VIRTIO_NET, PCI_VENDOR_ID_REDHAT_QUMRANET, VIRTIO_ID_NET, - 0x02, 0x00, 0x00, + PCI_CLASS_NETWORK_ETHERNET, 0x00, sizeof(struct virtio_net_config), sizeof(VirtIONet)); if (!n) Index: hw/piix_pci.c =================================================================== --- hw/piix_pci.c (revision 6490) +++ hw/piix_pci.c (working copy) @@ -195,8 +195,7 @@ PCIBus *i440fx_init(PCIDevice **pi440fx_state, qem pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL); pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_82441); d->config[0x08] = 0x02; // revision - d->config[0x0a] = 0x00; // class_sub = host2pci - d->config[0x0b] = 0x06; // class_base = PCI_bridge + pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); d->config[0x0e] = 0x00; // header_type d->config[0x72] = 0x02; /* SMRAM */ @@ -337,8 +336,7 @@ int piix3_init(PCIBus *bus, int devfn) pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1) - pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA - pci_conf[0x0b] = 0x06; // class_base = PCI_bridge + pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA); pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic piix3_reset(d); @@ -359,8 +357,7 @@ int piix4_init(PCIBus *bus, int devfn) pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_0); // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge - pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA - pci_conf[0x0b] = 0x06; // class_base = PCI_bridge + pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA); pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic piix4_reset(d); Index: hw/lsi53c895a.c =================================================================== --- hw/lsi53c895a.c (revision 6490) +++ hw/lsi53c895a.c (working copy) @@ -1979,7 +1979,7 @@ void *lsi_scsi_init(PCIBus *bus, int devfn) /* PCI device ID (word) */ pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_LSI_53C895A); /* PCI base class code */ - pci_conf[0x0b] = 0x01; + pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_SCSI); /* PCI subsystem ID */ pci_conf[0x2e] = 0x00; pci_conf[0x2f] = 0x10; Index: hw/virtio.c =================================================================== --- hw/virtio.c (revision 6490) +++ hw/virtio.c (working copy) @@ -811,9 +811,8 @@ void virtio_load(VirtIODevice *vdev, QEMUFile *f) VirtIODevice *virtio_init_pci(PCIBus *bus, const char *name, uint16_t vendor, uint16_t device, uint16_t subvendor, uint16_t subdevice, - uint8_t class_code, uint8_t subclass_code, - uint8_t pif, size_t config_size, - size_t struct_size) + uint16_t class_code, uint8_t pif, + size_t config_size, size_t struct_size) { VirtIODevice *vdev; PCIDevice *pci_dev; @@ -839,8 +838,7 @@ VirtIODevice *virtio_init_pci(PCIBus *bus, const c config[0x08] = VIRTIO_PCI_ABI_VERSION; config[0x09] = pif; - config[0x0a] = subclass_code; - config[0x0b] = class_code; + pci_config_set_class(config, class_code); config[0x0e] = 0x00; config[0x2c] = subvendor & 0xFF; Index: hw/virtio.h =================================================================== --- hw/virtio.h (revision 6490) +++ hw/virtio.h (working copy) @@ -92,9 +92,8 @@ struct VirtIODevice VirtIODevice *virtio_init_pci(PCIBus *bus, const char *name, uint16_t vendor, uint16_t device, uint16_t subvendor, uint16_t subdevice, - uint8_t class_code, uint8_t subclass_code, - uint8_t pif, size_t config_size, - size_t struct_size); + uint16_t class_code, uint8_t pif, + size_t config_size, size_t struct_size); VirtQueue *virtio_add_queue(VirtIODevice *vdev, int queue_size, void (*handle_output)(VirtIODevice *, Index: hw/es1370.c =================================================================== --- hw/es1370.c (revision 6490) +++ hw/es1370.c (working copy) @@ -1034,8 +1034,7 @@ int es1370_init (PCIBus *bus, AudioState *audio) pci_config_set_vendor_id(c, PCI_VENDOR_ID_ENSONIQ); pci_config_set_device_id(c, PCI_DEVICE_ID_ENSONIQ_ES1370); c[0x07] = 2 << 1; - c[0x0a] = 0x01; - c[0x0b] = 0x04; + pci_config_set_class(c, PCI_CLASS_MULTIMEDIA_AUDIO); #if 1 c[0x2c] = 0x42; Index: hw/macio.c =================================================================== --- hw/macio.c (revision 6490) +++ hw/macio.c (working copy) @@ -109,9 +109,7 @@ void macio_init (PCIBus *bus, int device_id, int i pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE); pci_config_set_device_id(d->config, device_id); - - d->config[0x0a] = 0x00; // class_sub = pci2pci - d->config[0x0b] = 0xff; // class_base = bridge + pci_config_set_class(d->config, PCI_CLASS_OTHERS << 8); d->config[0x0e] = 0x00; // header_type d->config[0x3d] = 0x01; // interrupt on pin 1 Index: hw/vga.c =================================================================== --- hw/vga.c (revision 6490) +++ hw/vga.c (working copy) @@ -2513,8 +2513,7 @@ int pci_vga_init(PCIBus *bus, uint8_t *vga_ram_bas // dummy VGA (same as Bochs ID) pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_QEMU); pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_QEMU_VGA); - pci_conf[0x0a] = 0x00; // VGA controller - pci_conf[0x0b] = 0x03; + pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA); pci_conf[0x0e] = 0x00; // header_type /* XXX: vga_ram_size must be a power of two */ Index: hw/sun4u.c =================================================================== --- hw/sun4u.c (revision 6490) +++ hw/sun4u.c (working copy) @@ -373,8 +373,7 @@ pci_ebus_init(PCIBus *bus, int devfn) s->config[0x07] = 0x03; // status = medium devsel s->config[0x08] = 0x01; // revision s->config[0x09] = 0x00; // programming i/f - s->config[0x0A] = 0x80; // class_sub = misc bridge - s->config[0x0B] = 0x06; // class_base = PCI_bridge + pci_config_set_class(d->config, PCI_CLASS_BRIDGE_OTHER); s->config[0x0D] = 0x0a; // latency_timer s->config[0x0E] = 0x00; // header_type Index: hw/ppc4xx_pci.c =================================================================== --- hw/ppc4xx_pci.c (revision 6490) +++ hw/ppc4xx_pci.c (working copy) @@ -382,8 +382,7 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pc pci_conf = controller->pci_dev->config; pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM); pci_config_set_device_id(pci_conf, 0x027f); // device_id - pci_conf[0x0a] = 0x80; // class_sub = other bridge type - pci_conf[0x0b] = 0x06; // class_base = PCI_bridge + pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER); /* CFGADDR */ index = cpu_register_io_memory(0, pci4xx_cfgaddr_read, Index: hw/gt64xxx.c =================================================================== --- hw/gt64xxx.c (revision 6490) +++ hw/gt64xxx.c (working copy) @@ -1146,8 +1146,7 @@ PCIBus *pci_gt64120_init(qemu_irq *pic) d->config[0x08] = 0x10; d->config[0x09] = 0x00; - d->config[0x0A] = 0x00; - d->config[0x0B] = 0x06; + pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); d->config[0x10] = 0x08; d->config[0x14] = 0x08; Index: hw/virtio-blk.c =================================================================== --- hw/virtio-blk.c (revision 6490) +++ hw/virtio-blk.c (working copy) @@ -305,7 +305,7 @@ void *virtio_blk_init(PCIBus *bus, BlockDriverStat PCI_DEVICE_ID_VIRTIO_BLOCK, PCI_VENDOR_ID_REDHAT_QUMRANET, VIRTIO_ID_BLOCK, - 0x01, 0x80, 0x00, + PCI_CLASS_STORAGE_OTHER, 0x00, sizeof(struct virtio_blk_config), sizeof(VirtIOBlock)); if (!s) return NULL; Index: hw/virtio-console.c =================================================================== --- hw/virtio-console.c (revision 6490) +++ hw/virtio-console.c (working copy) @@ -130,7 +130,7 @@ void *virtio_console_init(PCIBus *bus, CharDriverS PCI_DEVICE_ID_VIRTIO_CONSOLE, PCI_VENDOR_ID_REDHAT_QUMRANET, VIRTIO_ID_CONSOLE, - 0x03, 0x80, 0x00, + PCI_CLASS_DISPLAY_OTHER, 0x00, 0, sizeof(VirtIOConsole)); if (s == NULL) return NULL; Index: hw/e1000.c =================================================================== --- hw/e1000.c (revision 6490) +++ hw/e1000.c (working copy) @@ -1054,8 +1054,7 @@ pci_e1000_init(PCIBus *bus, NICInfo *nd, int devfn *(uint16_t *)(pci_conf+0x04) = cpu_to_le16(0x0407); *(uint16_t *)(pci_conf+0x06) = cpu_to_le16(0x0010); pci_conf[0x08] = 0x03; - pci_conf[0x0a] = 0x00; // ethernet network controller - pci_conf[0x0b] = 0x02; + pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); pci_conf[0x0c] = 0x10; pci_conf[0x3d] = 1; // interrupt pin 0 Index: hw/rtl8139.c =================================================================== --- hw/rtl8139.c (revision 6490) +++ hw/rtl8139.c (working copy) @@ -3429,8 +3429,7 @@ void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, in pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8139); pci_conf[0x04] = 0x05; /* command = I/O space, Bus Master */ pci_conf[0x08] = RTL8139_PCI_REVID; /* PCI revision ID; >=0x20 is for 8139C+ */ - pci_conf[0x0a] = 0x00; /* ethernet network controller */ - pci_conf[0x0b] = 0x02; + pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); pci_conf[0x0e] = 0x00; /* header_type */ pci_conf[0x3d] = 1; /* interrupt pin 0 */ pci_conf[0x34] = 0xdc; -- Stuart Brady