* [Qemu-devel] [PATCH 00/14] target-ppc: add floating-point AltiVec instructions
@ 2009-01-22 20:44 Nathan Froyd
2009-01-22 20:44 ` [Qemu-devel] [PATCH 01/14] Add f field to ppc_avr_t Nathan Froyd
` (13 more replies)
0 siblings, 14 replies; 47+ messages in thread
From: Nathan Froyd @ 2009-01-22 20:44 UTC (permalink / raw)
To: qemu-devel
This patch series adds support for nearly all of the floating-point
AltiVec instructions. It is broken up into separate patches for each
instruction "family" (add/sub, min/max, comparison instructions, etc.),
as the previous AltiVec integer instructions patch series was.
This patch series does not implement vexptefp and vlogefp, both of which
require functionality not implemented in the soft-float emulation code.
The instructions are straightforward, if tedious, to implement (find a
decent powf and log2f implementation, translate into soft-float
emulation calls).
-Nathan
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH 01/14] Add f field to ppc_avr_t
2009-01-22 20:44 [Qemu-devel] [PATCH 00/14] target-ppc: add floating-point AltiVec instructions Nathan Froyd
@ 2009-01-22 20:44 ` Nathan Froyd
2009-02-03 19:59 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 02/14] Add various NaN-handling macros Nathan Froyd
` (12 subsequent siblings)
13 siblings, 1 reply; 47+ messages in thread
From: Nathan Froyd @ 2009-01-22 20:44 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/cpu.h | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index f7a12da..dafe7f3 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -308,6 +308,7 @@ struct ppc_spr_t {
/* Altivec registers (128 bits) */
union ppc_avr_t {
+ float32 f[4];
uint8_t u8[16];
uint16_t u16[8];
uint32_t u32[4];
--
1.6.0.5
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH 02/14] Add various NaN-handling macros
2009-01-22 20:44 [Qemu-devel] [PATCH 00/14] target-ppc: add floating-point AltiVec instructions Nathan Froyd
2009-01-22 20:44 ` [Qemu-devel] [PATCH 01/14] Add f field to ppc_avr_t Nathan Froyd
@ 2009-01-22 20:44 ` Nathan Froyd
2009-02-03 19:41 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 03/14] Rename spe_status to vec_status Nathan Froyd
` (11 subsequent siblings)
13 siblings, 1 reply; 47+ messages in thread
From: Nathan Froyd @ 2009-01-22 20:44 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
These simplify the implementation of the floating-point Altivec
instructions and reduce clutter.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/op_helper.c | 21 +++++++++++++++++++++
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index d531dd8..9820040 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -1965,6 +1965,23 @@ target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_
for (index = ARRAY_SIZE(r->element)-1; index >= 0; index--)
#endif
+/* If X is a NaN, store the corresponding QNaN into RESULT. Otherwise,
+ * execute the following block. */
+#define DO_HANDLE_NAN(result, x) \
+ if (float32_is_nan(x) || float32_is_signaling_nan(x)) { \
+ CPU_FloatU __f; \
+ __f.f = x; \
+ __f.l = __f.l | (1 << 22); /* Set QNaN bit. */ \
+ result = __f.f; \
+ } else
+
+#define HANDLE_NAN1(result, x) \
+ DO_HANDLE_NAN(result, x)
+#define HANDLE_NAN2(result, x, y) \
+ DO_HANDLE_NAN(result, x) DO_HANDLE_NAN(result, y)
+#define HANDLE_NAN3(result, x, y, z) \
+ DO_HANDLE_NAN(result, x) DO_HANDLE_NAN(result, y) DO_HANDLE_NAN(result, z)
+
/* Saturating arithmetic helpers. */
#define SATCVT(from, to, from_type, to_type, min, max, use_min, use_max) \
static always_inline to_type cvt##from##to (from_type x, int *sat) \
@@ -2808,6 +2825,10 @@ VUPK(lsh, s32, s16, UPKLO)
#undef UPKHI
#undef UPKLO
+#undef DO_HANDLE_NAN
+#undef HANDLE_NAN1
+#undef HANDLE_NAN2
+#undef HANDLE_NAN3
#undef VECTOR_FOR_INORDER_I
#undef HI_IDX
#undef LO_IDX
--
1.6.0.5
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH 03/14] Rename spe_status to vec_status
2009-01-22 20:44 [Qemu-devel] [PATCH 00/14] target-ppc: add floating-point AltiVec instructions Nathan Froyd
2009-01-22 20:44 ` [Qemu-devel] [PATCH 01/14] Add f field to ppc_avr_t Nathan Froyd
2009-01-22 20:44 ` [Qemu-devel] [PATCH 02/14] Add various NaN-handling macros Nathan Froyd
@ 2009-01-22 20:44 ` Nathan Froyd
2009-02-03 19:59 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 04/14] Add calls to initialize VSCR on appropriate machines Nathan Froyd
` (10 subsequent siblings)
13 siblings, 1 reply; 47+ messages in thread
From: Nathan Froyd @ 2009-01-22 20:44 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
Only one of Altivec and SPE will be available on a given chip.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/cpu.h | 4 +-
target-ppc/op_helper.c | 112 ++++++++++++++++++++++++------------------------
2 files changed, 59 insertions(+), 57 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index dafe7f3..006f58d 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -611,8 +611,10 @@ struct CPUPPCState {
uint32_t vscr;
/* SPE registers */
uint64_t spe_acc;
- float_status spe_status;
uint32_t spe_fscr;
+ /* SPE and Altivec can share a status since they will never be used
+ * simultaneously */
+ float_status vec_status;
/* Internal devices resources */
/* Time base and decrementer */
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 9820040..3086bfd 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2882,7 +2882,7 @@ static always_inline uint32_t efscfsi (uint32_t val)
{
CPU_FloatU u;
- u.f = int32_to_float32(val, &env->spe_status);
+ u.f = int32_to_float32(val, &env->vec_status);
return u.l;
}
@@ -2891,7 +2891,7 @@ static always_inline uint32_t efscfui (uint32_t val)
{
CPU_FloatU u;
- u.f = uint32_to_float32(val, &env->spe_status);
+ u.f = uint32_to_float32(val, &env->vec_status);
return u.l;
}
@@ -2905,7 +2905,7 @@ static always_inline int32_t efsctsi (uint32_t val)
if (unlikely(float32_is_nan(u.f)))
return 0;
- return float32_to_int32(u.f, &env->spe_status);
+ return float32_to_int32(u.f, &env->vec_status);
}
static always_inline uint32_t efsctui (uint32_t val)
@@ -2917,7 +2917,7 @@ static always_inline uint32_t efsctui (uint32_t val)
if (unlikely(float32_is_nan(u.f)))
return 0;
- return float32_to_uint32(u.f, &env->spe_status);
+ return float32_to_uint32(u.f, &env->vec_status);
}
static always_inline uint32_t efsctsiz (uint32_t val)
@@ -2929,7 +2929,7 @@ static always_inline uint32_t efsctsiz (uint32_t val)
if (unlikely(float32_is_nan(u.f)))
return 0;
- return float32_to_int32_round_to_zero(u.f, &env->spe_status);
+ return float32_to_int32_round_to_zero(u.f, &env->vec_status);
}
static always_inline uint32_t efsctuiz (uint32_t val)
@@ -2941,7 +2941,7 @@ static always_inline uint32_t efsctuiz (uint32_t val)
if (unlikely(float32_is_nan(u.f)))
return 0;
- return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
+ return float32_to_uint32_round_to_zero(u.f, &env->vec_status);
}
static always_inline uint32_t efscfsf (uint32_t val)
@@ -2949,9 +2949,9 @@ static always_inline uint32_t efscfsf (uint32_t val)
CPU_FloatU u;
float32 tmp;
- u.f = int32_to_float32(val, &env->spe_status);
- tmp = int64_to_float32(1ULL << 32, &env->spe_status);
- u.f = float32_div(u.f, tmp, &env->spe_status);
+ u.f = int32_to_float32(val, &env->vec_status);
+ tmp = int64_to_float32(1ULL << 32, &env->vec_status);
+ u.f = float32_div(u.f, tmp, &env->vec_status);
return u.l;
}
@@ -2961,9 +2961,9 @@ static always_inline uint32_t efscfuf (uint32_t val)
CPU_FloatU u;
float32 tmp;
- u.f = uint32_to_float32(val, &env->spe_status);
- tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
- u.f = float32_div(u.f, tmp, &env->spe_status);
+ u.f = uint32_to_float32(val, &env->vec_status);
+ tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
+ u.f = float32_div(u.f, tmp, &env->vec_status);
return u.l;
}
@@ -2977,10 +2977,10 @@ static always_inline uint32_t efsctsf (uint32_t val)
/* NaN are not treated the same way IEEE 754 does */
if (unlikely(float32_is_nan(u.f)))
return 0;
- tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
- u.f = float32_mul(u.f, tmp, &env->spe_status);
+ tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
+ u.f = float32_mul(u.f, tmp, &env->vec_status);
- return float32_to_int32(u.f, &env->spe_status);
+ return float32_to_int32(u.f, &env->vec_status);
}
static always_inline uint32_t efsctuf (uint32_t val)
@@ -2992,10 +2992,10 @@ static always_inline uint32_t efsctuf (uint32_t val)
/* NaN are not treated the same way IEEE 754 does */
if (unlikely(float32_is_nan(u.f)))
return 0;
- tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
- u.f = float32_mul(u.f, tmp, &env->spe_status);
+ tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
+ u.f = float32_mul(u.f, tmp, &env->vec_status);
- return float32_to_uint32(u.f, &env->spe_status);
+ return float32_to_uint32(u.f, &env->vec_status);
}
#define HELPER_SPE_SINGLE_CONV(name) \
@@ -3057,7 +3057,7 @@ static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
CPU_FloatU u1, u2;
u1.l = op1;
u2.l = op2;
- u1.f = float32_add(u1.f, u2.f, &env->spe_status);
+ u1.f = float32_add(u1.f, u2.f, &env->vec_status);
return u1.l;
}
@@ -3066,7 +3066,7 @@ static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
CPU_FloatU u1, u2;
u1.l = op1;
u2.l = op2;
- u1.f = float32_sub(u1.f, u2.f, &env->spe_status);
+ u1.f = float32_sub(u1.f, u2.f, &env->vec_status);
return u1.l;
}
@@ -3075,7 +3075,7 @@ static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
CPU_FloatU u1, u2;
u1.l = op1;
u2.l = op2;
- u1.f = float32_mul(u1.f, u2.f, &env->spe_status);
+ u1.f = float32_mul(u1.f, u2.f, &env->vec_status);
return u1.l;
}
@@ -3084,7 +3084,7 @@ static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
CPU_FloatU u1, u2;
u1.l = op1;
u2.l = op2;
- u1.f = float32_div(u1.f, u2.f, &env->spe_status);
+ u1.f = float32_div(u1.f, u2.f, &env->vec_status);
return u1.l;
}
@@ -3123,7 +3123,7 @@ static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
CPU_FloatU u1, u2;
u1.l = op1;
u2.l = op2;
- return float32_lt(u1.f, u2.f, &env->spe_status) ? 4 : 0;
+ return float32_lt(u1.f, u2.f, &env->vec_status) ? 4 : 0;
}
static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
@@ -3131,7 +3131,7 @@ static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
CPU_FloatU u1, u2;
u1.l = op1;
u2.l = op2;
- return float32_le(u1.f, u2.f, &env->spe_status) ? 0 : 4;
+ return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 4;
}
static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
@@ -3139,7 +3139,7 @@ static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
CPU_FloatU u1, u2;
u1.l = op1;
u2.l = op2;
- return float32_eq(u1.f, u2.f, &env->spe_status) ? 4 : 0;
+ return float32_eq(u1.f, u2.f, &env->vec_status) ? 4 : 0;
}
static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
@@ -3206,7 +3206,7 @@ uint64_t helper_efdcfsi (uint32_t val)
{
CPU_DoubleU u;
- u.d = int32_to_float64(val, &env->spe_status);
+ u.d = int32_to_float64(val, &env->vec_status);
return u.ll;
}
@@ -3215,7 +3215,7 @@ uint64_t helper_efdcfsid (uint64_t val)
{
CPU_DoubleU u;
- u.d = int64_to_float64(val, &env->spe_status);
+ u.d = int64_to_float64(val, &env->vec_status);
return u.ll;
}
@@ -3224,7 +3224,7 @@ uint64_t helper_efdcfui (uint32_t val)
{
CPU_DoubleU u;
- u.d = uint32_to_float64(val, &env->spe_status);
+ u.d = uint32_to_float64(val, &env->vec_status);
return u.ll;
}
@@ -3233,7 +3233,7 @@ uint64_t helper_efdcfuid (uint64_t val)
{
CPU_DoubleU u;
- u.d = uint64_to_float64(val, &env->spe_status);
+ u.d = uint64_to_float64(val, &env->vec_status);
return u.ll;
}
@@ -3247,7 +3247,7 @@ uint32_t helper_efdctsi (uint64_t val)
if (unlikely(float64_is_nan(u.d)))
return 0;
- return float64_to_int32(u.d, &env->spe_status);
+ return float64_to_int32(u.d, &env->vec_status);
}
uint32_t helper_efdctui (uint64_t val)
@@ -3259,7 +3259,7 @@ uint32_t helper_efdctui (uint64_t val)
if (unlikely(float64_is_nan(u.d)))
return 0;
- return float64_to_uint32(u.d, &env->spe_status);
+ return float64_to_uint32(u.d, &env->vec_status);
}
uint32_t helper_efdctsiz (uint64_t val)
@@ -3271,7 +3271,7 @@ uint32_t helper_efdctsiz (uint64_t val)
if (unlikely(float64_is_nan(u.d)))
return 0;
- return float64_to_int32_round_to_zero(u.d, &env->spe_status);
+ return float64_to_int32_round_to_zero(u.d, &env->vec_status);
}
uint64_t helper_efdctsidz (uint64_t val)
@@ -3283,7 +3283,7 @@ uint64_t helper_efdctsidz (uint64_t val)
if (unlikely(float64_is_nan(u.d)))
return 0;
- return float64_to_int64_round_to_zero(u.d, &env->spe_status);
+ return float64_to_int64_round_to_zero(u.d, &env->vec_status);
}
uint32_t helper_efdctuiz (uint64_t val)
@@ -3295,7 +3295,7 @@ uint32_t helper_efdctuiz (uint64_t val)
if (unlikely(float64_is_nan(u.d)))
return 0;
- return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
+ return float64_to_uint32_round_to_zero(u.d, &env->vec_status);
}
uint64_t helper_efdctuidz (uint64_t val)
@@ -3307,7 +3307,7 @@ uint64_t helper_efdctuidz (uint64_t val)
if (unlikely(float64_is_nan(u.d)))
return 0;
- return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
+ return float64_to_uint64_round_to_zero(u.d, &env->vec_status);
}
uint64_t helper_efdcfsf (uint32_t val)
@@ -3315,9 +3315,9 @@ uint64_t helper_efdcfsf (uint32_t val)
CPU_DoubleU u;
float64 tmp;
- u.d = int32_to_float64(val, &env->spe_status);
- tmp = int64_to_float64(1ULL << 32, &env->spe_status);
- u.d = float64_div(u.d, tmp, &env->spe_status);
+ u.d = int32_to_float64(val, &env->vec_status);
+ tmp = int64_to_float64(1ULL << 32, &env->vec_status);
+ u.d = float64_div(u.d, tmp, &env->vec_status);
return u.ll;
}
@@ -3327,9 +3327,9 @@ uint64_t helper_efdcfuf (uint32_t val)
CPU_DoubleU u;
float64 tmp;
- u.d = uint32_to_float64(val, &env->spe_status);
- tmp = int64_to_float64(1ULL << 32, &env->spe_status);
- u.d = float64_div(u.d, tmp, &env->spe_status);
+ u.d = uint32_to_float64(val, &env->vec_status);
+ tmp = int64_to_float64(1ULL << 32, &env->vec_status);
+ u.d = float64_div(u.d, tmp, &env->vec_status);
return u.ll;
}
@@ -3343,10 +3343,10 @@ uint32_t helper_efdctsf (uint64_t val)
/* NaN are not treated the same way IEEE 754 does */
if (unlikely(float64_is_nan(u.d)))
return 0;
- tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
- u.d = float64_mul(u.d, tmp, &env->spe_status);
+ tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
+ u.d = float64_mul(u.d, tmp, &env->vec_status);
- return float64_to_int32(u.d, &env->spe_status);
+ return float64_to_int32(u.d, &env->vec_status);
}
uint32_t helper_efdctuf (uint64_t val)
@@ -3358,10 +3358,10 @@ uint32_t helper_efdctuf (uint64_t val)
/* NaN are not treated the same way IEEE 754 does */
if (unlikely(float64_is_nan(u.d)))
return 0;
- tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
- u.d = float64_mul(u.d, tmp, &env->spe_status);
+ tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
+ u.d = float64_mul(u.d, tmp, &env->vec_status);
- return float64_to_uint32(u.d, &env->spe_status);
+ return float64_to_uint32(u.d, &env->vec_status);
}
uint32_t helper_efscfd (uint64_t val)
@@ -3370,7 +3370,7 @@ uint32_t helper_efscfd (uint64_t val)
CPU_FloatU u2;
u1.ll = val;
- u2.f = float64_to_float32(u1.d, &env->spe_status);
+ u2.f = float64_to_float32(u1.d, &env->vec_status);
return u2.l;
}
@@ -3381,7 +3381,7 @@ uint64_t helper_efdcfs (uint32_t val)
CPU_FloatU u1;
u1.l = val;
- u2.d = float32_to_float64(u1.f, &env->spe_status);
+ u2.d = float32_to_float64(u1.f, &env->vec_status);
return u2.ll;
}
@@ -3392,7 +3392,7 @@ uint64_t helper_efdadd (uint64_t op1, uint64_t op2)
CPU_DoubleU u1, u2;
u1.ll = op1;
u2.ll = op2;
- u1.d = float64_add(u1.d, u2.d, &env->spe_status);
+ u1.d = float64_add(u1.d, u2.d, &env->vec_status);
return u1.ll;
}
@@ -3401,7 +3401,7 @@ uint64_t helper_efdsub (uint64_t op1, uint64_t op2)
CPU_DoubleU u1, u2;
u1.ll = op1;
u2.ll = op2;
- u1.d = float64_sub(u1.d, u2.d, &env->spe_status);
+ u1.d = float64_sub(u1.d, u2.d, &env->vec_status);
return u1.ll;
}
@@ -3410,7 +3410,7 @@ uint64_t helper_efdmul (uint64_t op1, uint64_t op2)
CPU_DoubleU u1, u2;
u1.ll = op1;
u2.ll = op2;
- u1.d = float64_mul(u1.d, u2.d, &env->spe_status);
+ u1.d = float64_mul(u1.d, u2.d, &env->vec_status);
return u1.ll;
}
@@ -3419,7 +3419,7 @@ uint64_t helper_efddiv (uint64_t op1, uint64_t op2)
CPU_DoubleU u1, u2;
u1.ll = op1;
u2.ll = op2;
- u1.d = float64_div(u1.d, u2.d, &env->spe_status);
+ u1.d = float64_div(u1.d, u2.d, &env->vec_status);
return u1.ll;
}
@@ -3429,7 +3429,7 @@ uint32_t helper_efdtstlt (uint64_t op1, uint64_t op2)
CPU_DoubleU u1, u2;
u1.ll = op1;
u2.ll = op2;
- return float64_lt(u1.d, u2.d, &env->spe_status) ? 4 : 0;
+ return float64_lt(u1.d, u2.d, &env->vec_status) ? 4 : 0;
}
uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
@@ -3437,7 +3437,7 @@ uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
CPU_DoubleU u1, u2;
u1.ll = op1;
u2.ll = op2;
- return float64_le(u1.d, u2.d, &env->spe_status) ? 0 : 4;
+ return float64_le(u1.d, u2.d, &env->vec_status) ? 0 : 4;
}
uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
@@ -3445,7 +3445,7 @@ uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
CPU_DoubleU u1, u2;
u1.ll = op1;
u2.ll = op2;
- return float64_eq(u1.d, u2.d, &env->spe_status) ? 4 : 0;
+ return float64_eq(u1.d, u2.d, &env->vec_status) ? 4 : 0;
}
uint32_t helper_efdcmplt (uint64_t op1, uint64_t op2)
--
1.6.0.5
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH 04/14] Add calls to initialize VSCR on appropriate machines
2009-01-22 20:44 [Qemu-devel] [PATCH 00/14] target-ppc: add floating-point AltiVec instructions Nathan Froyd
` (2 preceding siblings ...)
2009-01-22 20:44 ` [Qemu-devel] [PATCH 03/14] Rename spe_status to vec_status Nathan Froyd
@ 2009-01-22 20:44 ` Nathan Froyd
2009-02-03 19:59 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 05/14] Make mtvscr use a helper Nathan Froyd
` (9 subsequent siblings)
13 siblings, 1 reply; 47+ messages in thread
From: Nathan Froyd @ 2009-01-22 20:44 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/translate_init.c | 22 ++++++++++++++++++++++
1 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 5008a3a..d1722aa 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -471,6 +471,14 @@ static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
}
#endif
+static inline void vscr_init (CPUPPCState *env, uint32_t val)
+{
+ env->vscr = val;
+ /* Altivec always uses round-to-nearest */
+ set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
+ set_flush_to_zero(vscr_nj, &env->vec_status);
+}
+
#if defined(CONFIG_USER_ONLY)
#define spr_register(env, num, name, uea_read, uea_write, \
oea_read, oea_write, initial_value) \
@@ -1219,6 +1227,8 @@ static void gen_spr_74xx (CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+ /* Not strictly an SPR */
+ vscr_init(env, 0x00010000);
}
static void gen_l3_ctrl (CPUPPCState *env)
@@ -5918,6 +5928,9 @@ static void init_proc_970 (CPUPPCState *env)
env->icache_line_size = 128;
/* Allocate hardware IRQ controller */
ppc970_irq_init(env);
+ /* Can't find information on what this should be on reset. This
+ * value is the one used by 74xx processors. */
+ vscr_init(env, 0x00010000);
}
/* PowerPC 970FX (aka G5) */
@@ -6004,6 +6017,9 @@ static void init_proc_970FX (CPUPPCState *env)
env->icache_line_size = 128;
/* Allocate hardware IRQ controller */
ppc970_irq_init(env);
+ /* Can't find information on what this should be on reset. This
+ * value is the one used by 74xx processors. */
+ vscr_init(env, 0x00010000);
}
/* PowerPC 970 GX */
@@ -6090,6 +6106,9 @@ static void init_proc_970GX (CPUPPCState *env)
env->icache_line_size = 128;
/* Allocate hardware IRQ controller */
ppc970_irq_init(env);
+ /* Can't find information on what this should be on reset. This
+ * value is the one used by 74xx processors. */
+ vscr_init(env, 0x00010000);
}
/* PowerPC 970 MP */
@@ -6176,6 +6195,9 @@ static void init_proc_970MP (CPUPPCState *env)
env->icache_line_size = 128;
/* Allocate hardware IRQ controller */
ppc970_irq_init(env);
+ /* Can't find information on what this should be on reset. This
+ * value is the one used by 74xx processors. */
+ vscr_init(env, 0x00010000);
}
/* PowerPC 620 */
--
1.6.0.5
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH 05/14] Make mtvscr use a helper
2009-01-22 20:44 [Qemu-devel] [PATCH 00/14] target-ppc: add floating-point AltiVec instructions Nathan Froyd
` (3 preceding siblings ...)
2009-01-22 20:44 ` [Qemu-devel] [PATCH 04/14] Add calls to initialize VSCR on appropriate machines Nathan Froyd
@ 2009-01-22 20:44 ` Nathan Froyd
2009-02-03 19:59 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 06/14] Add v{max,min}fp instructions Nathan Froyd
` (8 subsequent siblings)
13 siblings, 1 reply; 47+ messages in thread
From: Nathan Froyd @ 2009-01-22 20:44 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
Do this so we can set float statuses once per mtvscr, rather than once
per Altivec instruction.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 1 +
target-ppc/op_helper.c | 10 ++++++++++
target-ppc/translate.c | 9 ++++-----
3 files changed, 15 insertions(+), 5 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 755bfba..8c04ba7 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -220,6 +220,7 @@ DEF_HELPER_4(vmsumuhs, void, avr, avr, avr, avr)
DEF_HELPER_4(vmsumshm, void, avr, avr, avr, avr)
DEF_HELPER_4(vmsumshs, void, avr, avr, avr, avr)
DEF_HELPER_4(vmladduhm, void, avr, avr, avr, avr)
+DEF_HELPER_1(mtvscr, void, avr);
DEF_HELPER_2(lvebx, void, avr, tl)
DEF_HELPER_2(lvehx, void, avr, tl)
DEF_HELPER_2(lvewx, void, avr, tl)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 3086bfd..107f977 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2067,6 +2067,16 @@ STVE(stvewx, stl, bswap32, u32)
#undef I
#undef LVE
+void helper_mtvscr (ppc_avr_t *r)
+{
+#if defined(WORDS_BIGENDIAN)
+ env->vscr = r->u32[3];
+#else
+ env->vscr = r->u32[0];
+#endif
+ set_flush_to_zero(vscr_nj, &env->vec_status);
+}
+
void helper_vaddcuw (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
{
int i;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 1bbe7f5..19abec1 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6268,15 +6268,14 @@ GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC)
GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC)
{
- TCGv_i32 t;
+ TCGv_ptr p;
if (unlikely(!ctx->altivec_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VPU);
return;
}
- t = tcg_temp_new_i32();
- tcg_gen_trunc_i64_i32(t, cpu_avrl[rD(ctx->opcode)]);
- tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, vscr));
- tcg_temp_free_i32(t);
+ p = gen_avr_ptr(rD(ctx->opcode));
+ gen_helper_mtvscr(p);
+ tcg_temp_free_ptr(p);
}
/* Logical operations */
--
1.6.0.5
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH 06/14] Add v{max,min}fp instructions
2009-01-22 20:44 [Qemu-devel] [PATCH 00/14] target-ppc: add floating-point AltiVec instructions Nathan Froyd
` (4 preceding siblings ...)
2009-01-22 20:44 ` [Qemu-devel] [PATCH 05/14] Make mtvscr use a helper Nathan Froyd
@ 2009-01-22 20:44 ` Nathan Froyd
2009-02-03 19:51 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 07/14] Add v{add,sub}fp instructions Nathan Froyd
` (7 subsequent siblings)
13 siblings, 1 reply; 47+ messages in thread
From: Nathan Froyd @ 2009-01-22 20:44 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 2 ++
target-ppc/op_helper.c | 19 +++++++++++++++++++
target-ppc/translate.c | 2 ++
3 files changed, 23 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 8c04ba7..ebdeabe 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -232,6 +232,8 @@ DEF_HELPER_3(vsum2sws, void, avr, avr, avr)
DEF_HELPER_3(vsum4sbs, void, avr, avr, avr)
DEF_HELPER_3(vsum4shs, void, avr, avr, avr)
DEF_HELPER_3(vsum4ubs, void, avr, avr, avr)
+DEF_HELPER_3(vmaxfp, void, avr, avr, avr)
+DEF_HELPER_3(vminfp, void, avr, avr, avr)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 107f977..717bbd4 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2252,6 +2252,25 @@ VMINMAX(uw, u32)
#undef VMINMAX_DO
#undef VMINMAX
+#define VMINMAXFP(suffix, relation) \
+ void helper_v##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+ { \
+ int i; \
+ for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
+ HANDLE_NAN2(r->f[i], a->f[i], b->f[i]) { \
+ int rel = float32_compare_quiet(a->f[i], b->f[i], &env->vec_status); \
+ if (rel == relation) { \
+ r->f[i] = a->f[i]; \
+ } else { \
+ r->f[i] = b->f[i]; \
+ } \
+ } \
+ } \
+ }
+VMINMAXFP(minfp, float_relation_less)
+VMINMAXFP(maxfp, float_relation_greater)
+#undef VMINMAXFP
+
void helper_vmladduhm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
{
int i;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 19abec1..35693e0 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6395,6 +6395,8 @@ GEN_VXFORM(vsum4sbs, 4, 28);
GEN_VXFORM(vsum4shs, 4, 25);
GEN_VXFORM(vsum2sws, 4, 26);
GEN_VXFORM(vsumsws, 4, 30);
+GEN_VXFORM(vmaxfp, 5, 10);
+GEN_VXFORM(vminfp, 5, 11);
#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH 07/14] Add v{add,sub}fp instructions
2009-01-22 20:44 [Qemu-devel] [PATCH 00/14] target-ppc: add floating-point AltiVec instructions Nathan Froyd
` (5 preceding siblings ...)
2009-01-22 20:44 ` [Qemu-devel] [PATCH 06/14] Add v{max,min}fp instructions Nathan Froyd
@ 2009-01-22 20:44 ` Nathan Froyd
2009-02-03 19:52 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 08/14] Add vmaddfp and vnmsubfp instructions Nathan Froyd
` (6 subsequent siblings)
13 siblings, 1 reply; 47+ messages in thread
From: Nathan Froyd @ 2009-01-22 20:44 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
Split up vaddfp and vsubfp so that we can properly handle magnitude
subtraction of infinities.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 2 ++
target-ppc/op_helper.c | 27 +++++++++++++++++++++++++++
target-ppc/translate.c | 2 ++
3 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index ebdeabe..a5d1972 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -232,6 +232,8 @@ DEF_HELPER_3(vsum2sws, void, avr, avr, avr)
DEF_HELPER_3(vsum4sbs, void, avr, avr, avr)
DEF_HELPER_3(vsum4shs, void, avr, avr, avr)
DEF_HELPER_3(vsum4ubs, void, avr, avr, avr)
+DEF_HELPER_3(vaddfp, void, avr, avr, avr)
+DEF_HELPER_3(vsubfp, void, avr, avr, avr)
DEF_HELPER_3(vmaxfp, void, avr, avr, avr)
DEF_HELPER_3(vminfp, void, avr, avr, avr)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 717bbd4..d952113 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2102,6 +2102,33 @@ VARITH(uwm, u32)
#undef VARITH_DO
#undef VARITH
+void helper_vaddfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(r->f); i++) {
+ HANDLE_NAN2(r->f[i], a->f[i], b->f[i]) {
+ r->f[i] = float32_add(a->f[i], b->f[i], &env->vec_status);
+ }
+ }
+}
+
+void helper_vsubfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(r->f); i++) {
+ HANDLE_NAN2(r->f[i], a->f[i], b->f[i]) {
+ if (unlikely(float32_is_infinity(a->f[i]) &&
+ float32_is_infinity(b->f[i]) &&
+ float32_is_neg(a->f[i]) == float32_is_neg(b->f[i]))) {
+ /* Magnitude subtraction of infinities */
+ r->u32[i] = 0x7fc00000;
+ } else {
+ r->f[i] = float32_sub(a->f[i], b->f[i], &env->vec_status);
+ }
+ }
+ }
+}
+
#define VARITHSAT_CASE(type, op, cvt, element) \
{ \
type result = (type)a->element[i] op (type)b->element[i]; \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 35693e0..6ff46e0 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6395,6 +6395,8 @@ GEN_VXFORM(vsum4sbs, 4, 28);
GEN_VXFORM(vsum4shs, 4, 25);
GEN_VXFORM(vsum2sws, 4, 26);
GEN_VXFORM(vsumsws, 4, 30);
+GEN_VXFORM(vaddfp, 5, 0);
+GEN_VXFORM(vsubfp, 5, 1);
GEN_VXFORM(vmaxfp, 5, 10);
GEN_VXFORM(vminfp, 5, 11);
--
1.6.0.5
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH 08/14] Add vmaddfp and vnmsubfp instructions
2009-01-22 20:44 [Qemu-devel] [PATCH 00/14] target-ppc: add floating-point AltiVec instructions Nathan Froyd
` (6 preceding siblings ...)
2009-01-22 20:44 ` [Qemu-devel] [PATCH 07/14] Add v{add,sub}fp instructions Nathan Froyd
@ 2009-01-22 20:44 ` Nathan Froyd
2009-02-04 10:39 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 09/14] Add vcmp{eq,ge,gt,b}fp{,.} instructions Nathan Froyd
` (5 subsequent siblings)
13 siblings, 1 reply; 47+ messages in thread
From: Nathan Froyd @ 2009-01-22 20:44 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
Do the computation in higher precision and check for invalid operation
conditions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 2 +
target-ppc/op_helper.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++
target-ppc/translate.c | 1 +
3 files changed, 57 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index a5d1972..6f5d6a6 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -236,6 +236,8 @@ DEF_HELPER_3(vaddfp, void, avr, avr, avr)
DEF_HELPER_3(vsubfp, void, avr, avr, avr)
DEF_HELPER_3(vmaxfp, void, avr, avr, avr)
DEF_HELPER_3(vminfp, void, avr, avr, avr)
+DEF_HELPER_4(vmaddfp, void, avr, avr, avr, avr)
+DEF_HELPER_4(vnmsubfp, void, avr, avr, avr, avr)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index d952113..532a08a 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2223,6 +2223,29 @@ VCMP(gtsw, >, s32)
#undef VCMP_DO
#undef VCMP
+void helper_vmaddfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(r->f); i++) {
+ HANDLE_NAN3(r->f[i], a->f[i], b->f[i], c->f[i]) {
+ /* Need to do the computation in higher precision and round
+ * once at the end. */
+ float64 af, cf;
+ af = float32_to_float64(a->f[i], &env->vec_status);
+ cf = float32_to_float64(c->f[i], &env->vec_status);
+ if ((float64_is_infinity(af) && float64_is_zero(cf)) ||
+ (float64_is_zero(af) && float64_is_infinity(cf))) {
+ r->u32[i] = 0x7fc00000;
+ } else {
+ float64 t = float64_mul(af, cf, &env->vec_status);
+ float64 bf = float32_to_float64(b->f[i], &env->vec_status);
+ t = float64_add(t, bf, &env->vec_status);
+ r->f[i] = float64_to_float32(t, &env->vec_status);
+ }
+ }
+ }
+}
+
void helper_vmhaddshs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
{
int sat = 0;
@@ -2460,6 +2483,37 @@ VMUL(uh, u16, u32)
#undef VMUL_DO
#undef VMUL
+void helper_vnmsubfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(r->f); i++) {
+ HANDLE_NAN3(r->f[i], a->f[i], b->f[i], c->f[i]) {
+ /* Need to do the computation is higher precision and round
+ * once at the end. */
+ float64 af, cf;
+ af = float32_to_float64(a->f[i], &env->vec_status);
+ cf = float32_to_float64(c->f[i], &env->vec_status);
+ if ((float64_is_infinity(af) && float64_is_zero(cf)) ||
+ (float64_is_zero(af) && float64_is_infinity(cf))) {
+ r->u32[i] = 0x7fc00000;
+ } else {
+ float64 t = float64_mul(af, cf, &env->vec_status);
+ float64 bf = float32_to_float64(b->f[i], &env->vec_status);
+ if (unlikely(float64_is_infinity(t) &&
+ float64_is_infinity(bf) &&
+ float64_is_neg(t) == float64_is_neg(bf))) {
+ /* Magnitude subtraction of infinities */
+ r->u32[i] = 0x7fc00000;
+ } else {
+ t = float64_sub(t, bf, &env->vec_status);
+ t = float64_chs(t);
+ r->f[i] = float64_to_float32(t, &env->vec_status);
+ }
+ }
+ }
+ }
+}
+
void helper_vperm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
{
ppc_avr_t result;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 6ff46e0..8b67333 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6577,6 +6577,7 @@ GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
GEN_VAFORM_PAIRED(vsel, vperm, 21)
+GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
/*** SPE extension ***/
/* Register moves */
--
1.6.0.5
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH 09/14] Add vcmp{eq,ge,gt,b}fp{,.} instructions
2009-01-22 20:44 [Qemu-devel] [PATCH 00/14] target-ppc: add floating-point AltiVec instructions Nathan Froyd
` (7 preceding siblings ...)
2009-01-22 20:44 ` [Qemu-devel] [PATCH 08/14] Add vmaddfp and vnmsubfp instructions Nathan Froyd
@ 2009-01-22 20:44 ` Nathan Froyd
2009-02-04 14:12 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 10/14] Add vrfi{m,n,p,z} instructions Nathan Froyd
` (4 subsequent siblings)
13 siblings, 1 reply; 47+ messages in thread
From: Nathan Froyd @ 2009-01-22 20:44 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 8 +++++
target-ppc/op_helper.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++++
target-ppc/translate.c | 4 +++
3 files changed, 80 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 6f5d6a6..ff4b0db 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -132,6 +132,10 @@ DEF_HELPER_3(vcmpgtuw, void, avr, avr, avr)
DEF_HELPER_3(vcmpgtsb, void, avr, avr, avr)
DEF_HELPER_3(vcmpgtsh, void, avr, avr, avr)
DEF_HELPER_3(vcmpgtsw, void, avr, avr, avr)
+DEF_HELPER_3(vcmpeqfp, void, avr, avr, avr)
+DEF_HELPER_3(vcmpgefp, void, avr, avr, avr)
+DEF_HELPER_3(vcmpgtfp, void, avr, avr, avr)
+DEF_HELPER_3(vcmpbfp, void, avr, avr, avr)
DEF_HELPER_3(vcmpequb_dot, void, avr, avr, avr)
DEF_HELPER_3(vcmpequh_dot, void, avr, avr, avr)
DEF_HELPER_3(vcmpequw_dot, void, avr, avr, avr)
@@ -141,6 +145,10 @@ DEF_HELPER_3(vcmpgtuw_dot, void, avr, avr, avr)
DEF_HELPER_3(vcmpgtsb_dot, void, avr, avr, avr)
DEF_HELPER_3(vcmpgtsh_dot, void, avr, avr, avr)
DEF_HELPER_3(vcmpgtsw_dot, void, avr, avr, avr)
+DEF_HELPER_3(vcmpeqfp_dot, void, avr, avr, avr)
+DEF_HELPER_3(vcmpgefp_dot, void, avr, avr, avr)
+DEF_HELPER_3(vcmpgtfp_dot, void, avr, avr, avr)
+DEF_HELPER_3(vcmpbfp_dot, void, avr, avr, avr)
DEF_HELPER_3(vmrglb, void, avr, avr, avr)
DEF_HELPER_3(vmrglh, void, avr, avr, avr)
DEF_HELPER_3(vmrglw, void, avr, avr, avr)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 532a08a..4b62735 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2223,6 +2223,74 @@ VCMP(gtsw, >, s32)
#undef VCMP_DO
#undef VCMP
+#define VCMPFP_DO(suffix, compare, order, record) \
+ void helper_vcmp##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+ { \
+ uint32_t ones = (uint32_t)-1; \
+ uint32_t all = ones; \
+ uint32_t none = 0; \
+ int i; \
+ for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
+ uint32_t result; \
+ int rel = float32_compare_quiet(a->f[i], b->f[i], &env->vec_status); \
+ if (rel == float_relation_unordered) { \
+ result = 0; \
+ } else if (rel compare order) { \
+ result = ones; \
+ } else { \
+ result = 0; \
+ } \
+ r->u32[i] = result; \
+ all &= result; \
+ none |= result; \
+ } \
+ if (record) { \
+ env->crf[6] = ((all != 0) << 3) | ((none == 0) << 1); \
+ } \
+ }
+#define VCMPFP(suffix, compare, order) \
+ VCMPFP_DO(suffix, compare, order, 0) \
+ VCMPFP_DO(suffix##_dot, compare, order, 1)
+VCMPFP(eqfp, ==, float_relation_equal)
+VCMPFP(gefp, !=, float_relation_less)
+VCMPFP(gtfp, ==, float_relation_greater)
+#undef VCMPFP_DO
+#undef VCMPFP
+
+static always_inline void vcmpbfp_internal (ppc_avr_t *r, ppc_avr_t *a,
+ ppc_avr_t *b, int record)
+{
+ int i;
+ int all_in = 0;
+ for (i = 0; i < ARRAY_SIZE(r->f); i++) {
+ int le_rel = float32_compare_quiet(a->f[i], b->f[i], &env->vec_status);
+ if (le_rel == float_relation_unordered) {
+ r->u32[i] = 0xc0000000;
+ /* ALL_IN does not need to be updated here. */
+ } else {
+ float32 bneg = float32_chs(b->f[i]);
+ int ge_rel = float32_compare_quiet(a->f[i], bneg, &env->vec_status);
+ int le = le_rel != float_relation_greater;
+ int ge = ge_rel != float_relation_less;
+ r->u32[i] = ((!le) << 31) | ((!ge) << 30);
+ all_in |= (!le | !ge);
+ }
+ }
+ if (record) {
+ env->crf[6] = (all_in == 0) << 1;
+ }
+}
+
+void helper_vcmpbfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ vcmpbfp_internal(r, a, b, 0);
+}
+
+void helper_vcmpbfp_dot (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ vcmpbfp_internal(r, a, b, 1);
+}
+
void helper_vmaddfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
{
int i;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 8b67333..312cbcb 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6430,6 +6430,10 @@ GEN_VXRFORM(vcmpgtsw, 3, 14)
GEN_VXRFORM(vcmpgtub, 3, 8)
GEN_VXRFORM(vcmpgtuh, 3, 9)
GEN_VXRFORM(vcmpgtuw, 3, 10)
+GEN_VXRFORM(vcmpeqfp, 3, 3)
+GEN_VXRFORM(vcmpgefp, 3, 7)
+GEN_VXRFORM(vcmpgtfp, 3, 11)
+GEN_VXRFORM(vcmpbfp, 3, 3)
#define GEN_VXFORM_SIMM(name, opc2, opc3) \
GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH 10/14] Add vrfi{m,n,p,z} instructions
2009-01-22 20:44 [Qemu-devel] [PATCH 00/14] target-ppc: add floating-point AltiVec instructions Nathan Froyd
` (8 preceding siblings ...)
2009-01-22 20:44 ` [Qemu-devel] [PATCH 09/14] Add vcmp{eq,ge,gt,b}fp{,.} instructions Nathan Froyd
@ 2009-01-22 20:44 ` Nathan Froyd
2009-02-04 13:53 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 11/14] Add vcf{u,s}x instructions Nathan Froyd
` (3 subsequent siblings)
13 siblings, 1 reply; 47+ messages in thread
From: Nathan Froyd @ 2009-01-22 20:44 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 4 ++++
target-ppc/op_helper.c | 18 ++++++++++++++++++
target-ppc/translate.c | 4 ++++
3 files changed, 26 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index ff4b0db..3c2756e 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -244,6 +244,10 @@ DEF_HELPER_3(vaddfp, void, avr, avr, avr)
DEF_HELPER_3(vsubfp, void, avr, avr, avr)
DEF_HELPER_3(vmaxfp, void, avr, avr, avr)
DEF_HELPER_3(vminfp, void, avr, avr, avr)
+DEF_HELPER_2(vrfim, void, avr, avr)
+DEF_HELPER_2(vrfin, void, avr, avr)
+DEF_HELPER_2(vrfip, void, avr, avr)
+DEF_HELPER_2(vrfiz, void, avr, avr)
DEF_HELPER_4(vmaddfp, void, avr, avr, avr, avr)
DEF_HELPER_4(vnmsubfp, void, avr, avr, avr, avr)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 4b62735..cd35868 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2658,6 +2658,24 @@ VPK(uwum, u32, u16, I, 0)
#undef VPK
#undef PKBIG
+#define VRFI(suffix, rounding) \
+ void helper_vrfi##suffix (ppc_avr_t *r, ppc_avr_t *b) \
+ { \
+ int i; \
+ float_status s = env->vec_status; \
+ set_float_rounding_mode(rounding, &s); \
+ for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
+ HANDLE_NAN1(r->f[i], b->f[i]) { \
+ r->f[i] = float32_round_to_int (b->f[i], &s); \
+ } \
+ } \
+ }
+VRFI(n, float_round_nearest_even)
+VRFI(m, float_round_down)
+VRFI(p, float_round_up)
+VRFI(z, float_round_to_zero)
+#undef VRFI
+
#define VROTATE(suffix, element) \
void helper_vrl##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 312cbcb..2c111af 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6476,6 +6476,10 @@ GEN_VXFORM_NOA(vupklsb, 7, 10);
GEN_VXFORM_NOA(vupklsh, 7, 11);
GEN_VXFORM_NOA(vupkhpx, 7, 13);
GEN_VXFORM_NOA(vupklpx, 7, 15);
+GEN_VXFORM_NOA(vrfim, 5, 8);
+GEN_VXFORM_NOA(vrfin, 5, 9);
+GEN_VXFORM_NOA(vrfip, 5, 10);
+GEN_VXFORM_NOA(vrfiz, 5, 11);
#define GEN_VXFORM_SIMM(name, opc2, opc3) \
GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH 11/14] Add vcf{u,s}x instructions
2009-01-22 20:44 [Qemu-devel] [PATCH 00/14] target-ppc: add floating-point AltiVec instructions Nathan Froyd
` (9 preceding siblings ...)
2009-01-22 20:44 ` [Qemu-devel] [PATCH 10/14] Add vrfi{m,n,p,z} instructions Nathan Froyd
@ 2009-01-22 20:44 ` Nathan Froyd
2009-02-04 13:54 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 12/14] Add vct{u,s}xs instructions Nathan Froyd
` (2 subsequent siblings)
13 siblings, 1 reply; 47+ messages in thread
From: Nathan Froyd @ 2009-01-22 20:44 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 2 ++
target-ppc/op_helper.c | 13 +++++++++++++
target-ppc/translate.c | 2 ++
3 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 3c2756e..6e25d94 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -250,6 +250,8 @@ DEF_HELPER_2(vrfip, void, avr, avr)
DEF_HELPER_2(vrfiz, void, avr, avr)
DEF_HELPER_4(vmaddfp, void, avr, avr, avr, avr)
DEF_HELPER_4(vnmsubfp, void, avr, avr, avr, avr)
+DEF_HELPER_3(vcfux, void, avr, avr, i32)
+DEF_HELPER_3(vcfsx, void, avr, avr, i32)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index cd35868..32ea54f 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2187,6 +2187,19 @@ VAVG(w, s32, int64_t, u32, uint64_t)
#undef VAVG_DO
#undef VAVG
+#define VCF(suffix, cvt, element) \
+ void helper_vcf##suffix (ppc_avr_t *r, ppc_avr_t *b, uint32_t uim) \
+ { \
+ int i; \
+ for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
+ float32 t = cvt(b->element[i], &env->vec_status); \
+ r->f[i] = float32_scalbn (t, -uim, &env->vec_status); \
+ } \
+ }
+VCF(ux, uint32_to_float32, u32)
+VCF(sx, int32_to_float32, s32)
+#undef VCF
+
#define VCMP_DO(suffix, compare, element, record) \
void helper_vcmp##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 2c111af..e0cbf45 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6518,6 +6518,8 @@ GEN_VXFORM_NOA(vrfiz, 5, 11);
GEN_VXFORM_UIMM(vspltb, 6, 8);
GEN_VXFORM_UIMM(vsplth, 6, 9);
GEN_VXFORM_UIMM(vspltw, 6, 10);
+GEN_VXFORM_UIMM(vcfux, 5, 12);
+GEN_VXFORM_UIMM(vcfsx, 5, 13);
GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
{
--
1.6.0.5
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH 12/14] Add vct{u,s}xs instructions
2009-01-22 20:44 [Qemu-devel] [PATCH 00/14] target-ppc: add floating-point AltiVec instructions Nathan Froyd
` (10 preceding siblings ...)
2009-01-22 20:44 ` [Qemu-devel] [PATCH 11/14] Add vcf{u,s}x instructions Nathan Froyd
@ 2009-01-22 20:44 ` Nathan Froyd
2009-02-04 14:46 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 13/14] Add vrefp instruction Nathan Froyd
2009-01-22 20:44 ` [Qemu-devel] [PATCH 14/14] Add vrsqrtefp instruction Nathan Froyd
13 siblings, 1 reply; 47+ messages in thread
From: Nathan Froyd @ 2009-01-22 20:44 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 2 ++
target-ppc/op_helper.c | 25 +++++++++++++++++++++++++
target-ppc/translate.c | 2 ++
3 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 6e25d94..a463787 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -252,6 +252,8 @@ DEF_HELPER_4(vmaddfp, void, avr, avr, avr, avr)
DEF_HELPER_4(vnmsubfp, void, avr, avr, avr, avr)
DEF_HELPER_3(vcfux, void, avr, avr, i32)
DEF_HELPER_3(vcfsx, void, avr, avr, i32)
+DEF_HELPER_3(vctuxs, void, avr, avr, i32)
+DEF_HELPER_3(vctsxs, void, avr, avr, i32)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 32ea54f..e1022ab 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2304,6 +2304,31 @@ void helper_vcmpbfp_dot (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
vcmpbfp_internal(r, a, b, 1);
}
+#define VCT(suffix, type, floatcvt, satcvt, element) \
+ void helper_vct##suffix (ppc_avr_t *r, ppc_avr_t *b, uint32_t uim) \
+ { \
+ int i; \
+ int sat = 0; \
+ for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
+ if (float32_is_nan(b->f[i]) || \
+ float32_is_signaling_nan(b->f[i])) { \
+ r->element[i] = 0; \
+ } else { \
+ float64 t = float32_to_float64(b->f[i], &env->vec_status); \
+ type j; \
+ t = float64_scalbn(t, uim, &env->vec_status); \
+ j = floatcvt(t, &env->vec_status); \
+ r->element[i] = satcvt(j, &sat); \
+ } \
+ } \
+ if (sat) { \
+ env->vscr |= (1 << VSCR_SAT); \
+ } \
+ }
+VCT(uxs, uint64_t, float64_to_uint64, cvtuduw, u32)
+VCT(sxs, int64_t, float64_to_int64, cvtsdsw, s32)
+#undef VCT
+
void helper_vmaddfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
{
int i;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index e0cbf45..81011a2 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6520,6 +6520,8 @@ GEN_VXFORM_UIMM(vsplth, 6, 9);
GEN_VXFORM_UIMM(vspltw, 6, 10);
GEN_VXFORM_UIMM(vcfux, 5, 12);
GEN_VXFORM_UIMM(vcfsx, 5, 13);
+GEN_VXFORM_UIMM(vctuxs, 5, 14);
+GEN_VXFORM_UIMM(vctsxs, 5, 15);
GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
{
--
1.6.0.5
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH 13/14] Add vrefp instruction
2009-01-22 20:44 [Qemu-devel] [PATCH 00/14] target-ppc: add floating-point AltiVec instructions Nathan Froyd
` (11 preceding siblings ...)
2009-01-22 20:44 ` [Qemu-devel] [PATCH 12/14] Add vct{u,s}xs instructions Nathan Froyd
@ 2009-01-22 20:44 ` Nathan Froyd
2009-02-04 13:56 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 14/14] Add vrsqrtefp instruction Nathan Froyd
13 siblings, 1 reply; 47+ messages in thread
From: Nathan Froyd @ 2009-01-22 20:44 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 1 +
target-ppc/op_helper.c | 27 +++++++++++++++++++++++++++
target-ppc/translate.c | 1 +
3 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index a463787..516cee0 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -244,6 +244,7 @@ DEF_HELPER_3(vaddfp, void, avr, avr, avr)
DEF_HELPER_3(vsubfp, void, avr, avr, avr)
DEF_HELPER_3(vmaxfp, void, avr, avr, avr)
DEF_HELPER_3(vminfp, void, avr, avr, avr)
+DEF_HELPER_2(vrefp, void, avr, avr)
DEF_HELPER_2(vrfim, void, avr, avr)
DEF_HELPER_2(vrfin, void, avr, avr)
DEF_HELPER_2(vrfip, void, avr, avr)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index e1022ab..8055e1a 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2696,6 +2696,33 @@ VPK(uwum, u32, u16, I, 0)
#undef VPK
#undef PKBIG
+void helper_vrefp (ppc_avr_t *r, ppc_avr_t *b)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(r->f); i++) {
+ HANDLE_NAN1(r->f[i], b->f[i]) {
+ if (float32_is_infinity(b->f[i])) {
+ if (float32_is_neg(b->f[i])) {
+ r->f[i] = float32_chs(float32_zero);
+ } else {
+ r->f[i] = float32_zero;
+ }
+ } else if (float32_is_zero(b->f[i])) {
+ if (float32_is_neg(b->f[i])) {
+ /* Negative infinity */
+ r->u32[i] = 0xff800000;
+ } else {
+ /* Positive infinity */
+ r->u32[i] = 0x7f800000;
+ }
+ } else {
+ float32 one = int32_to_float32(1, &env->vec_status);
+ r->f[i] = float32_div(one, b->f[i], &env->vec_status);
+ }
+ }
+ }
+}
+
#define VRFI(suffix, rounding) \
void helper_vrfi##suffix (ppc_avr_t *r, ppc_avr_t *b) \
{ \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 81011a2..01a4f11 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6476,6 +6476,7 @@ GEN_VXFORM_NOA(vupklsb, 7, 10);
GEN_VXFORM_NOA(vupklsh, 7, 11);
GEN_VXFORM_NOA(vupkhpx, 7, 13);
GEN_VXFORM_NOA(vupklpx, 7, 15);
+GEN_VXFORM_NOA(vrefp, 5, 4);
GEN_VXFORM_NOA(vrfim, 5, 8);
GEN_VXFORM_NOA(vrfin, 5, 9);
GEN_VXFORM_NOA(vrfip, 5, 10);
--
1.6.0.5
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH 14/14] Add vrsqrtefp instruction
2009-01-22 20:44 [Qemu-devel] [PATCH 00/14] target-ppc: add floating-point AltiVec instructions Nathan Froyd
` (12 preceding siblings ...)
2009-01-22 20:44 ` [Qemu-devel] [PATCH 13/14] Add vrefp instruction Nathan Froyd
@ 2009-01-22 20:44 ` Nathan Froyd
2009-02-04 13:56 ` Aurelien Jarno
13 siblings, 1 reply; 47+ messages in thread
From: Nathan Froyd @ 2009-01-22 20:44 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 1 +
target-ppc/op_helper.c | 28 ++++++++++++++++++++++++++++
target-ppc/translate.c | 1 +
3 files changed, 30 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 516cee0..179f077 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -245,6 +245,7 @@ DEF_HELPER_3(vsubfp, void, avr, avr, avr)
DEF_HELPER_3(vmaxfp, void, avr, avr, avr)
DEF_HELPER_3(vminfp, void, avr, avr, avr)
DEF_HELPER_2(vrefp, void, avr, avr)
+DEF_HELPER_2(vrsqrtefp, void, avr, avr)
DEF_HELPER_2(vrfim, void, avr, avr)
DEF_HELPER_2(vrfin, void, avr, avr)
DEF_HELPER_2(vrfip, void, avr, avr)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 8055e1a..4ef0b1c 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2756,6 +2756,34 @@ VROTATE(h, u16)
VROTATE(w, u32)
#undef VROTATE
+void helper_vrsqrtefp (ppc_avr_t *r, ppc_avr_t *b)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(r->f); i++) {
+ HANDLE_NAN1(r->f[i], b->f[i]) {
+ if (float32_is_zero(b->f[i])) {
+ if (float32_is_neg(b->f[i])) {
+ /* Negative infinity */
+ r->u32[i] = 0xff800000;
+ } else {
+ /* Positive infinity */
+ r->u32[i] = 0x7f800000;
+ }
+ } else if (float32_is_neg(b->f[i])) {
+ /* Canonical QNaN */
+ r->u32[i] = 0x7fc00000;
+ } else if (float32_is_infinity(b->f[i])) {
+ /* Negative infinity handled earlier */
+ r->f[i] = float32_zero;
+ } else {
+ float32 one = int32_to_float32(1, &env->vec_status);
+ float32 t = float32_sqrt(b->f[i], &env->vec_status);
+ r->f[i] = float32_div(one, t, &env->vec_status);
+ }
+ }
+ }
+}
+
void helper_vsel (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
{
r->u64[0] = (a->u64[0] & ~c->u64[0]) | (b->u64[0] & c->u64[0]);
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 01a4f11..1c44c59 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6477,6 +6477,7 @@ GEN_VXFORM_NOA(vupklsh, 7, 11);
GEN_VXFORM_NOA(vupkhpx, 7, 13);
GEN_VXFORM_NOA(vupklpx, 7, 15);
GEN_VXFORM_NOA(vrefp, 5, 4);
+GEN_VXFORM_NOA(vrsqrtefp, 5, 5);
GEN_VXFORM_NOA(vrfim, 5, 8);
GEN_VXFORM_NOA(vrfin, 5, 9);
GEN_VXFORM_NOA(vrfip, 5, 10);
--
1.6.0.5
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 02/14] Add various NaN-handling macros
2009-01-22 20:44 ` [Qemu-devel] [PATCH 02/14] Add various NaN-handling macros Nathan Froyd
@ 2009-02-03 19:41 ` Aurelien Jarno
2009-02-03 20:19 ` Nathan Froyd
0 siblings, 1 reply; 47+ messages in thread
From: Aurelien Jarno @ 2009-02-03 19:41 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
On Thu, Jan 22, 2009 at 12:44:02PM -0800, Nathan Froyd wrote:
> These simplify the implementation of the floating-point Altivec
> instructions and reduce clutter.
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/op_helper.c | 21 +++++++++++++++++++++
> 1 files changed, 21 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index d531dd8..9820040 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -1965,6 +1965,23 @@ target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_
> for (index = ARRAY_SIZE(r->element)-1; index >= 0; index--)
> #endif
>
> +/* If X is a NaN, store the corresponding QNaN into RESULT. Otherwise,
> + * execute the following block. */
> +#define DO_HANDLE_NAN(result, x) \
> + if (float32_is_nan(x) || float32_is_signaling_nan(x)) { \
> + CPU_FloatU __f; \
> + __f.f = x; \
> + __f.l = __f.l | (1 << 22); /* Set QNaN bit. */ \
> + result = __f.f; \
> + } else
> +
> +#define HANDLE_NAN1(result, x) \
> + DO_HANDLE_NAN(result, x)
> +#define HANDLE_NAN2(result, x, y) \
> + DO_HANDLE_NAN(result, x) DO_HANDLE_NAN(result, y)
> +#define HANDLE_NAN3(result, x, y, z) \
> + DO_HANDLE_NAN(result, x) DO_HANDLE_NAN(result, y) DO_HANDLE_NAN(result, z)
> +
> /* Saturating arithmetic helpers. */
> #define SATCVT(from, to, from_type, to_type, min, max, use_min, use_max) \
> static always_inline to_type cvt##from##to (from_type x, int *sat) \
> @@ -2808,6 +2825,10 @@ VUPK(lsh, s32, s16, UPKLO)
> #undef UPKHI
> #undef UPKLO
>
> +#undef DO_HANDLE_NAN
> +#undef HANDLE_NAN1
> +#undef HANDLE_NAN2
> +#undef HANDLE_NAN3
> #undef VECTOR_FOR_INORDER_I
> #undef HI_IDX
> #undef LO_IDX
This is something already handled by the softfloat code. You should use
set_default_nan_mode(1, &env->vec_status) to get this behavior. This
could probably done directly in the init code.
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 06/14] Add v{max,min}fp instructions
2009-01-22 20:44 ` [Qemu-devel] [PATCH 06/14] Add v{max,min}fp instructions Nathan Froyd
@ 2009-02-03 19:51 ` Aurelien Jarno
2009-02-04 9:06 ` Aurelien Jarno
0 siblings, 1 reply; 47+ messages in thread
From: Aurelien Jarno @ 2009-02-03 19:51 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
On Thu, Jan 22, 2009 at 12:44:06PM -0800, Nathan Froyd wrote:
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/helper.h | 2 ++
> target-ppc/op_helper.c | 19 +++++++++++++++++++
> target-ppc/translate.c | 2 ++
> 3 files changed, 23 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 8c04ba7..ebdeabe 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -232,6 +232,8 @@ DEF_HELPER_3(vsum2sws, void, avr, avr, avr)
> DEF_HELPER_3(vsum4sbs, void, avr, avr, avr)
> DEF_HELPER_3(vsum4shs, void, avr, avr, avr)
> DEF_HELPER_3(vsum4ubs, void, avr, avr, avr)
> +DEF_HELPER_3(vmaxfp, void, avr, avr, avr)
> +DEF_HELPER_3(vminfp, void, avr, avr, avr)
>
> DEF_HELPER_1(efscfsi, i32, i32)
> DEF_HELPER_1(efscfui, i32, i32)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index 107f977..717bbd4 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2252,6 +2252,25 @@ VMINMAX(uw, u32)
> #undef VMINMAX_DO
> #undef VMINMAX
>
> +#define VMINMAXFP(suffix, relation) \
> + void helper_v##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> + { \
> + int i; \
> + for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
> + HANDLE_NAN2(r->f[i], a->f[i], b->f[i]) { \
> + int rel = float32_compare_quiet(a->f[i], b->f[i], &env->vec_status); \
Given that we only care about lower / greater, I wonder if it would be
better to use float32_lt_quiet and reversing the arguments.
> + if (rel == relation) { \
> + r->f[i] = a->f[i]; \
> + } else { \
> + r->f[i] = b->f[i]; \
> + } \
> + } \
> + } \
> + }
> +VMINMAXFP(minfp, float_relation_less)
> +VMINMAXFP(maxfp, float_relation_greater)
> +#undef VMINMAXFP
> +
> void helper_vmladduhm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> {
> int i;
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 19abec1..35693e0 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6395,6 +6395,8 @@ GEN_VXFORM(vsum4sbs, 4, 28);
> GEN_VXFORM(vsum4shs, 4, 25);
> GEN_VXFORM(vsum2sws, 4, 26);
> GEN_VXFORM(vsumsws, 4, 30);
> +GEN_VXFORM(vmaxfp, 5, 10);
> +GEN_VXFORM(vminfp, 5, 11);
>
> #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
> GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
> --
> 1.6.0.5
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 07/14] Add v{add,sub}fp instructions
2009-01-22 20:44 ` [Qemu-devel] [PATCH 07/14] Add v{add,sub}fp instructions Nathan Froyd
@ 2009-02-03 19:52 ` Aurelien Jarno
2009-02-03 20:34 ` Nathan Froyd
2009-02-08 22:39 ` Nathan Froyd
0 siblings, 2 replies; 47+ messages in thread
From: Aurelien Jarno @ 2009-02-03 19:52 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
On Thu, Jan 22, 2009 at 12:44:07PM -0800, Nathan Froyd wrote:
> Split up vaddfp and vsubfp so that we can properly handle magnitude
> subtraction of infinities.
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/helper.h | 2 ++
> target-ppc/op_helper.c | 27 +++++++++++++++++++++++++++
> target-ppc/translate.c | 2 ++
> 3 files changed, 31 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index ebdeabe..a5d1972 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -232,6 +232,8 @@ DEF_HELPER_3(vsum2sws, void, avr, avr, avr)
> DEF_HELPER_3(vsum4sbs, void, avr, avr, avr)
> DEF_HELPER_3(vsum4shs, void, avr, avr, avr)
> DEF_HELPER_3(vsum4ubs, void, avr, avr, avr)
> +DEF_HELPER_3(vaddfp, void, avr, avr, avr)
> +DEF_HELPER_3(vsubfp, void, avr, avr, avr)
> DEF_HELPER_3(vmaxfp, void, avr, avr, avr)
> DEF_HELPER_3(vminfp, void, avr, avr, avr)
>
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index 717bbd4..d952113 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2102,6 +2102,33 @@ VARITH(uwm, u32)
> #undef VARITH_DO
> #undef VARITH
>
> +void helper_vaddfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
> +{
> + int i;
> + for (i = 0; i < ARRAY_SIZE(r->f); i++) {
> + HANDLE_NAN2(r->f[i], a->f[i], b->f[i]) {
> + r->f[i] = float32_add(a->f[i], b->f[i], &env->vec_status);
> + }
> + }
> +}
> +
> +void helper_vsubfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
> +{
> + int i;
> + for (i = 0; i < ARRAY_SIZE(r->f); i++) {
> + HANDLE_NAN2(r->f[i], a->f[i], b->f[i]) {
> + if (unlikely(float32_is_infinity(a->f[i]) &&
> + float32_is_infinity(b->f[i]) &&
> + float32_is_neg(a->f[i]) == float32_is_neg(b->f[i]))) {
> + /* Magnitude subtraction of infinities */
> + r->u32[i] = 0x7fc00000;
I think this case is already handled by the softfloat code.
> + } else {
> + r->f[i] = float32_sub(a->f[i], b->f[i], &env->vec_status);
> + }
> + }
> + }
> +}
> +
> #define VARITHSAT_CASE(type, op, cvt, element) \
> { \
> type result = (type)a->element[i] op (type)b->element[i]; \
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 35693e0..6ff46e0 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6395,6 +6395,8 @@ GEN_VXFORM(vsum4sbs, 4, 28);
> GEN_VXFORM(vsum4shs, 4, 25);
> GEN_VXFORM(vsum2sws, 4, 26);
> GEN_VXFORM(vsumsws, 4, 30);
> +GEN_VXFORM(vaddfp, 5, 0);
> +GEN_VXFORM(vsubfp, 5, 1);
> GEN_VXFORM(vmaxfp, 5, 10);
> GEN_VXFORM(vminfp, 5, 11);
>
> --
> 1.6.0.5
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 01/14] Add f field to ppc_avr_t
2009-01-22 20:44 ` [Qemu-devel] [PATCH 01/14] Add f field to ppc_avr_t Nathan Froyd
@ 2009-02-03 19:59 ` Aurelien Jarno
0 siblings, 0 replies; 47+ messages in thread
From: Aurelien Jarno @ 2009-02-03 19:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
On Thu, Jan 22, 2009 at 12:44:01PM -0800, Nathan Froyd wrote:
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Thanks, applied.
> ---
> target-ppc/cpu.h | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index f7a12da..dafe7f3 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -308,6 +308,7 @@ struct ppc_spr_t {
>
> /* Altivec registers (128 bits) */
> union ppc_avr_t {
> + float32 f[4];
> uint8_t u8[16];
> uint16_t u16[8];
> uint32_t u32[4];
> --
> 1.6.0.5
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 03/14] Rename spe_status to vec_status
2009-01-22 20:44 ` [Qemu-devel] [PATCH 03/14] Rename spe_status to vec_status Nathan Froyd
@ 2009-02-03 19:59 ` Aurelien Jarno
0 siblings, 0 replies; 47+ messages in thread
From: Aurelien Jarno @ 2009-02-03 19:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
On Thu, Jan 22, 2009 at 12:44:03PM -0800, Nathan Froyd wrote:
> Only one of Altivec and SPE will be available on a given chip.
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Thanks, applied.
> ---
> target-ppc/cpu.h | 4 +-
> target-ppc/op_helper.c | 112 ++++++++++++++++++++++++------------------------
> 2 files changed, 59 insertions(+), 57 deletions(-)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index dafe7f3..006f58d 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -611,8 +611,10 @@ struct CPUPPCState {
> uint32_t vscr;
> /* SPE registers */
> uint64_t spe_acc;
> - float_status spe_status;
> uint32_t spe_fscr;
> + /* SPE and Altivec can share a status since they will never be used
> + * simultaneously */
> + float_status vec_status;
>
> /* Internal devices resources */
> /* Time base and decrementer */
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index 9820040..3086bfd 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2882,7 +2882,7 @@ static always_inline uint32_t efscfsi (uint32_t val)
> {
> CPU_FloatU u;
>
> - u.f = int32_to_float32(val, &env->spe_status);
> + u.f = int32_to_float32(val, &env->vec_status);
>
> return u.l;
> }
> @@ -2891,7 +2891,7 @@ static always_inline uint32_t efscfui (uint32_t val)
> {
> CPU_FloatU u;
>
> - u.f = uint32_to_float32(val, &env->spe_status);
> + u.f = uint32_to_float32(val, &env->vec_status);
>
> return u.l;
> }
> @@ -2905,7 +2905,7 @@ static always_inline int32_t efsctsi (uint32_t val)
> if (unlikely(float32_is_nan(u.f)))
> return 0;
>
> - return float32_to_int32(u.f, &env->spe_status);
> + return float32_to_int32(u.f, &env->vec_status);
> }
>
> static always_inline uint32_t efsctui (uint32_t val)
> @@ -2917,7 +2917,7 @@ static always_inline uint32_t efsctui (uint32_t val)
> if (unlikely(float32_is_nan(u.f)))
> return 0;
>
> - return float32_to_uint32(u.f, &env->spe_status);
> + return float32_to_uint32(u.f, &env->vec_status);
> }
>
> static always_inline uint32_t efsctsiz (uint32_t val)
> @@ -2929,7 +2929,7 @@ static always_inline uint32_t efsctsiz (uint32_t val)
> if (unlikely(float32_is_nan(u.f)))
> return 0;
>
> - return float32_to_int32_round_to_zero(u.f, &env->spe_status);
> + return float32_to_int32_round_to_zero(u.f, &env->vec_status);
> }
>
> static always_inline uint32_t efsctuiz (uint32_t val)
> @@ -2941,7 +2941,7 @@ static always_inline uint32_t efsctuiz (uint32_t val)
> if (unlikely(float32_is_nan(u.f)))
> return 0;
>
> - return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
> + return float32_to_uint32_round_to_zero(u.f, &env->vec_status);
> }
>
> static always_inline uint32_t efscfsf (uint32_t val)
> @@ -2949,9 +2949,9 @@ static always_inline uint32_t efscfsf (uint32_t val)
> CPU_FloatU u;
> float32 tmp;
>
> - u.f = int32_to_float32(val, &env->spe_status);
> - tmp = int64_to_float32(1ULL << 32, &env->spe_status);
> - u.f = float32_div(u.f, tmp, &env->spe_status);
> + u.f = int32_to_float32(val, &env->vec_status);
> + tmp = int64_to_float32(1ULL << 32, &env->vec_status);
> + u.f = float32_div(u.f, tmp, &env->vec_status);
>
> return u.l;
> }
> @@ -2961,9 +2961,9 @@ static always_inline uint32_t efscfuf (uint32_t val)
> CPU_FloatU u;
> float32 tmp;
>
> - u.f = uint32_to_float32(val, &env->spe_status);
> - tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
> - u.f = float32_div(u.f, tmp, &env->spe_status);
> + u.f = uint32_to_float32(val, &env->vec_status);
> + tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
> + u.f = float32_div(u.f, tmp, &env->vec_status);
>
> return u.l;
> }
> @@ -2977,10 +2977,10 @@ static always_inline uint32_t efsctsf (uint32_t val)
> /* NaN are not treated the same way IEEE 754 does */
> if (unlikely(float32_is_nan(u.f)))
> return 0;
> - tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
> - u.f = float32_mul(u.f, tmp, &env->spe_status);
> + tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
> + u.f = float32_mul(u.f, tmp, &env->vec_status);
>
> - return float32_to_int32(u.f, &env->spe_status);
> + return float32_to_int32(u.f, &env->vec_status);
> }
>
> static always_inline uint32_t efsctuf (uint32_t val)
> @@ -2992,10 +2992,10 @@ static always_inline uint32_t efsctuf (uint32_t val)
> /* NaN are not treated the same way IEEE 754 does */
> if (unlikely(float32_is_nan(u.f)))
> return 0;
> - tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
> - u.f = float32_mul(u.f, tmp, &env->spe_status);
> + tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
> + u.f = float32_mul(u.f, tmp, &env->vec_status);
>
> - return float32_to_uint32(u.f, &env->spe_status);
> + return float32_to_uint32(u.f, &env->vec_status);
> }
>
> #define HELPER_SPE_SINGLE_CONV(name) \
> @@ -3057,7 +3057,7 @@ static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
> CPU_FloatU u1, u2;
> u1.l = op1;
> u2.l = op2;
> - u1.f = float32_add(u1.f, u2.f, &env->spe_status);
> + u1.f = float32_add(u1.f, u2.f, &env->vec_status);
> return u1.l;
> }
>
> @@ -3066,7 +3066,7 @@ static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
> CPU_FloatU u1, u2;
> u1.l = op1;
> u2.l = op2;
> - u1.f = float32_sub(u1.f, u2.f, &env->spe_status);
> + u1.f = float32_sub(u1.f, u2.f, &env->vec_status);
> return u1.l;
> }
>
> @@ -3075,7 +3075,7 @@ static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
> CPU_FloatU u1, u2;
> u1.l = op1;
> u2.l = op2;
> - u1.f = float32_mul(u1.f, u2.f, &env->spe_status);
> + u1.f = float32_mul(u1.f, u2.f, &env->vec_status);
> return u1.l;
> }
>
> @@ -3084,7 +3084,7 @@ static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
> CPU_FloatU u1, u2;
> u1.l = op1;
> u2.l = op2;
> - u1.f = float32_div(u1.f, u2.f, &env->spe_status);
> + u1.f = float32_div(u1.f, u2.f, &env->vec_status);
> return u1.l;
> }
>
> @@ -3123,7 +3123,7 @@ static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
> CPU_FloatU u1, u2;
> u1.l = op1;
> u2.l = op2;
> - return float32_lt(u1.f, u2.f, &env->spe_status) ? 4 : 0;
> + return float32_lt(u1.f, u2.f, &env->vec_status) ? 4 : 0;
> }
>
> static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
> @@ -3131,7 +3131,7 @@ static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
> CPU_FloatU u1, u2;
> u1.l = op1;
> u2.l = op2;
> - return float32_le(u1.f, u2.f, &env->spe_status) ? 0 : 4;
> + return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 4;
> }
>
> static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
> @@ -3139,7 +3139,7 @@ static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
> CPU_FloatU u1, u2;
> u1.l = op1;
> u2.l = op2;
> - return float32_eq(u1.f, u2.f, &env->spe_status) ? 4 : 0;
> + return float32_eq(u1.f, u2.f, &env->vec_status) ? 4 : 0;
> }
>
> static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
> @@ -3206,7 +3206,7 @@ uint64_t helper_efdcfsi (uint32_t val)
> {
> CPU_DoubleU u;
>
> - u.d = int32_to_float64(val, &env->spe_status);
> + u.d = int32_to_float64(val, &env->vec_status);
>
> return u.ll;
> }
> @@ -3215,7 +3215,7 @@ uint64_t helper_efdcfsid (uint64_t val)
> {
> CPU_DoubleU u;
>
> - u.d = int64_to_float64(val, &env->spe_status);
> + u.d = int64_to_float64(val, &env->vec_status);
>
> return u.ll;
> }
> @@ -3224,7 +3224,7 @@ uint64_t helper_efdcfui (uint32_t val)
> {
> CPU_DoubleU u;
>
> - u.d = uint32_to_float64(val, &env->spe_status);
> + u.d = uint32_to_float64(val, &env->vec_status);
>
> return u.ll;
> }
> @@ -3233,7 +3233,7 @@ uint64_t helper_efdcfuid (uint64_t val)
> {
> CPU_DoubleU u;
>
> - u.d = uint64_to_float64(val, &env->spe_status);
> + u.d = uint64_to_float64(val, &env->vec_status);
>
> return u.ll;
> }
> @@ -3247,7 +3247,7 @@ uint32_t helper_efdctsi (uint64_t val)
> if (unlikely(float64_is_nan(u.d)))
> return 0;
>
> - return float64_to_int32(u.d, &env->spe_status);
> + return float64_to_int32(u.d, &env->vec_status);
> }
>
> uint32_t helper_efdctui (uint64_t val)
> @@ -3259,7 +3259,7 @@ uint32_t helper_efdctui (uint64_t val)
> if (unlikely(float64_is_nan(u.d)))
> return 0;
>
> - return float64_to_uint32(u.d, &env->spe_status);
> + return float64_to_uint32(u.d, &env->vec_status);
> }
>
> uint32_t helper_efdctsiz (uint64_t val)
> @@ -3271,7 +3271,7 @@ uint32_t helper_efdctsiz (uint64_t val)
> if (unlikely(float64_is_nan(u.d)))
> return 0;
>
> - return float64_to_int32_round_to_zero(u.d, &env->spe_status);
> + return float64_to_int32_round_to_zero(u.d, &env->vec_status);
> }
>
> uint64_t helper_efdctsidz (uint64_t val)
> @@ -3283,7 +3283,7 @@ uint64_t helper_efdctsidz (uint64_t val)
> if (unlikely(float64_is_nan(u.d)))
> return 0;
>
> - return float64_to_int64_round_to_zero(u.d, &env->spe_status);
> + return float64_to_int64_round_to_zero(u.d, &env->vec_status);
> }
>
> uint32_t helper_efdctuiz (uint64_t val)
> @@ -3295,7 +3295,7 @@ uint32_t helper_efdctuiz (uint64_t val)
> if (unlikely(float64_is_nan(u.d)))
> return 0;
>
> - return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
> + return float64_to_uint32_round_to_zero(u.d, &env->vec_status);
> }
>
> uint64_t helper_efdctuidz (uint64_t val)
> @@ -3307,7 +3307,7 @@ uint64_t helper_efdctuidz (uint64_t val)
> if (unlikely(float64_is_nan(u.d)))
> return 0;
>
> - return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
> + return float64_to_uint64_round_to_zero(u.d, &env->vec_status);
> }
>
> uint64_t helper_efdcfsf (uint32_t val)
> @@ -3315,9 +3315,9 @@ uint64_t helper_efdcfsf (uint32_t val)
> CPU_DoubleU u;
> float64 tmp;
>
> - u.d = int32_to_float64(val, &env->spe_status);
> - tmp = int64_to_float64(1ULL << 32, &env->spe_status);
> - u.d = float64_div(u.d, tmp, &env->spe_status);
> + u.d = int32_to_float64(val, &env->vec_status);
> + tmp = int64_to_float64(1ULL << 32, &env->vec_status);
> + u.d = float64_div(u.d, tmp, &env->vec_status);
>
> return u.ll;
> }
> @@ -3327,9 +3327,9 @@ uint64_t helper_efdcfuf (uint32_t val)
> CPU_DoubleU u;
> float64 tmp;
>
> - u.d = uint32_to_float64(val, &env->spe_status);
> - tmp = int64_to_float64(1ULL << 32, &env->spe_status);
> - u.d = float64_div(u.d, tmp, &env->spe_status);
> + u.d = uint32_to_float64(val, &env->vec_status);
> + tmp = int64_to_float64(1ULL << 32, &env->vec_status);
> + u.d = float64_div(u.d, tmp, &env->vec_status);
>
> return u.ll;
> }
> @@ -3343,10 +3343,10 @@ uint32_t helper_efdctsf (uint64_t val)
> /* NaN are not treated the same way IEEE 754 does */
> if (unlikely(float64_is_nan(u.d)))
> return 0;
> - tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
> - u.d = float64_mul(u.d, tmp, &env->spe_status);
> + tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
> + u.d = float64_mul(u.d, tmp, &env->vec_status);
>
> - return float64_to_int32(u.d, &env->spe_status);
> + return float64_to_int32(u.d, &env->vec_status);
> }
>
> uint32_t helper_efdctuf (uint64_t val)
> @@ -3358,10 +3358,10 @@ uint32_t helper_efdctuf (uint64_t val)
> /* NaN are not treated the same way IEEE 754 does */
> if (unlikely(float64_is_nan(u.d)))
> return 0;
> - tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
> - u.d = float64_mul(u.d, tmp, &env->spe_status);
> + tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
> + u.d = float64_mul(u.d, tmp, &env->vec_status);
>
> - return float64_to_uint32(u.d, &env->spe_status);
> + return float64_to_uint32(u.d, &env->vec_status);
> }
>
> uint32_t helper_efscfd (uint64_t val)
> @@ -3370,7 +3370,7 @@ uint32_t helper_efscfd (uint64_t val)
> CPU_FloatU u2;
>
> u1.ll = val;
> - u2.f = float64_to_float32(u1.d, &env->spe_status);
> + u2.f = float64_to_float32(u1.d, &env->vec_status);
>
> return u2.l;
> }
> @@ -3381,7 +3381,7 @@ uint64_t helper_efdcfs (uint32_t val)
> CPU_FloatU u1;
>
> u1.l = val;
> - u2.d = float32_to_float64(u1.f, &env->spe_status);
> + u2.d = float32_to_float64(u1.f, &env->vec_status);
>
> return u2.ll;
> }
> @@ -3392,7 +3392,7 @@ uint64_t helper_efdadd (uint64_t op1, uint64_t op2)
> CPU_DoubleU u1, u2;
> u1.ll = op1;
> u2.ll = op2;
> - u1.d = float64_add(u1.d, u2.d, &env->spe_status);
> + u1.d = float64_add(u1.d, u2.d, &env->vec_status);
> return u1.ll;
> }
>
> @@ -3401,7 +3401,7 @@ uint64_t helper_efdsub (uint64_t op1, uint64_t op2)
> CPU_DoubleU u1, u2;
> u1.ll = op1;
> u2.ll = op2;
> - u1.d = float64_sub(u1.d, u2.d, &env->spe_status);
> + u1.d = float64_sub(u1.d, u2.d, &env->vec_status);
> return u1.ll;
> }
>
> @@ -3410,7 +3410,7 @@ uint64_t helper_efdmul (uint64_t op1, uint64_t op2)
> CPU_DoubleU u1, u2;
> u1.ll = op1;
> u2.ll = op2;
> - u1.d = float64_mul(u1.d, u2.d, &env->spe_status);
> + u1.d = float64_mul(u1.d, u2.d, &env->vec_status);
> return u1.ll;
> }
>
> @@ -3419,7 +3419,7 @@ uint64_t helper_efddiv (uint64_t op1, uint64_t op2)
> CPU_DoubleU u1, u2;
> u1.ll = op1;
> u2.ll = op2;
> - u1.d = float64_div(u1.d, u2.d, &env->spe_status);
> + u1.d = float64_div(u1.d, u2.d, &env->vec_status);
> return u1.ll;
> }
>
> @@ -3429,7 +3429,7 @@ uint32_t helper_efdtstlt (uint64_t op1, uint64_t op2)
> CPU_DoubleU u1, u2;
> u1.ll = op1;
> u2.ll = op2;
> - return float64_lt(u1.d, u2.d, &env->spe_status) ? 4 : 0;
> + return float64_lt(u1.d, u2.d, &env->vec_status) ? 4 : 0;
> }
>
> uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
> @@ -3437,7 +3437,7 @@ uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
> CPU_DoubleU u1, u2;
> u1.ll = op1;
> u2.ll = op2;
> - return float64_le(u1.d, u2.d, &env->spe_status) ? 0 : 4;
> + return float64_le(u1.d, u2.d, &env->vec_status) ? 0 : 4;
> }
>
> uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
> @@ -3445,7 +3445,7 @@ uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
> CPU_DoubleU u1, u2;
> u1.ll = op1;
> u2.ll = op2;
> - return float64_eq(u1.d, u2.d, &env->spe_status) ? 4 : 0;
> + return float64_eq(u1.d, u2.d, &env->vec_status) ? 4 : 0;
> }
>
> uint32_t helper_efdcmplt (uint64_t op1, uint64_t op2)
> --
> 1.6.0.5
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 04/14] Add calls to initialize VSCR on appropriate machines
2009-01-22 20:44 ` [Qemu-devel] [PATCH 04/14] Add calls to initialize VSCR on appropriate machines Nathan Froyd
@ 2009-02-03 19:59 ` Aurelien Jarno
0 siblings, 0 replies; 47+ messages in thread
From: Aurelien Jarno @ 2009-02-03 19:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
On Thu, Jan 22, 2009 at 12:44:04PM -0800, Nathan Froyd wrote:
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Thanks, applied.
> ---
> target-ppc/translate_init.c | 22 ++++++++++++++++++++++
> 1 files changed, 22 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 5008a3a..d1722aa 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -471,6 +471,14 @@ static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
> }
> #endif
>
> +static inline void vscr_init (CPUPPCState *env, uint32_t val)
> +{
> + env->vscr = val;
> + /* Altivec always uses round-to-nearest */
> + set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
> + set_flush_to_zero(vscr_nj, &env->vec_status);
> +}
> +
> #if defined(CONFIG_USER_ONLY)
> #define spr_register(env, num, name, uea_read, uea_write, \
> oea_read, oea_write, initial_value) \
> @@ -1219,6 +1227,8 @@ static void gen_spr_74xx (CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> + /* Not strictly an SPR */
> + vscr_init(env, 0x00010000);
> }
>
> static void gen_l3_ctrl (CPUPPCState *env)
> @@ -5918,6 +5928,9 @@ static void init_proc_970 (CPUPPCState *env)
> env->icache_line_size = 128;
> /* Allocate hardware IRQ controller */
> ppc970_irq_init(env);
> + /* Can't find information on what this should be on reset. This
> + * value is the one used by 74xx processors. */
> + vscr_init(env, 0x00010000);
> }
>
> /* PowerPC 970FX (aka G5) */
> @@ -6004,6 +6017,9 @@ static void init_proc_970FX (CPUPPCState *env)
> env->icache_line_size = 128;
> /* Allocate hardware IRQ controller */
> ppc970_irq_init(env);
> + /* Can't find information on what this should be on reset. This
> + * value is the one used by 74xx processors. */
> + vscr_init(env, 0x00010000);
> }
>
> /* PowerPC 970 GX */
> @@ -6090,6 +6106,9 @@ static void init_proc_970GX (CPUPPCState *env)
> env->icache_line_size = 128;
> /* Allocate hardware IRQ controller */
> ppc970_irq_init(env);
> + /* Can't find information on what this should be on reset. This
> + * value is the one used by 74xx processors. */
> + vscr_init(env, 0x00010000);
> }
>
> /* PowerPC 970 MP */
> @@ -6176,6 +6195,9 @@ static void init_proc_970MP (CPUPPCState *env)
> env->icache_line_size = 128;
> /* Allocate hardware IRQ controller */
> ppc970_irq_init(env);
> + /* Can't find information on what this should be on reset. This
> + * value is the one used by 74xx processors. */
> + vscr_init(env, 0x00010000);
> }
>
> /* PowerPC 620 */
> --
> 1.6.0.5
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 05/14] Make mtvscr use a helper
2009-01-22 20:44 ` [Qemu-devel] [PATCH 05/14] Make mtvscr use a helper Nathan Froyd
@ 2009-02-03 19:59 ` Aurelien Jarno
0 siblings, 0 replies; 47+ messages in thread
From: Aurelien Jarno @ 2009-02-03 19:59 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
On Thu, Jan 22, 2009 at 12:44:05PM -0800, Nathan Froyd wrote:
> Do this so we can set float statuses once per mtvscr, rather than once
> per Altivec instruction.
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Thanks, applied.
> ---
> target-ppc/helper.h | 1 +
> target-ppc/op_helper.c | 10 ++++++++++
> target-ppc/translate.c | 9 ++++-----
> 3 files changed, 15 insertions(+), 5 deletions(-)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 755bfba..8c04ba7 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -220,6 +220,7 @@ DEF_HELPER_4(vmsumuhs, void, avr, avr, avr, avr)
> DEF_HELPER_4(vmsumshm, void, avr, avr, avr, avr)
> DEF_HELPER_4(vmsumshs, void, avr, avr, avr, avr)
> DEF_HELPER_4(vmladduhm, void, avr, avr, avr, avr)
> +DEF_HELPER_1(mtvscr, void, avr);
> DEF_HELPER_2(lvebx, void, avr, tl)
> DEF_HELPER_2(lvehx, void, avr, tl)
> DEF_HELPER_2(lvewx, void, avr, tl)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index 3086bfd..107f977 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2067,6 +2067,16 @@ STVE(stvewx, stl, bswap32, u32)
> #undef I
> #undef LVE
>
> +void helper_mtvscr (ppc_avr_t *r)
> +{
> +#if defined(WORDS_BIGENDIAN)
> + env->vscr = r->u32[3];
> +#else
> + env->vscr = r->u32[0];
> +#endif
> + set_flush_to_zero(vscr_nj, &env->vec_status);
> +}
> +
> void helper_vaddcuw (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
> {
> int i;
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 1bbe7f5..19abec1 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6268,15 +6268,14 @@ GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC)
>
> GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC)
> {
> - TCGv_i32 t;
> + TCGv_ptr p;
> if (unlikely(!ctx->altivec_enabled)) {
> gen_exception(ctx, POWERPC_EXCP_VPU);
> return;
> }
> - t = tcg_temp_new_i32();
> - tcg_gen_trunc_i64_i32(t, cpu_avrl[rD(ctx->opcode)]);
> - tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, vscr));
> - tcg_temp_free_i32(t);
> + p = gen_avr_ptr(rD(ctx->opcode));
> + gen_helper_mtvscr(p);
> + tcg_temp_free_ptr(p);
> }
>
> /* Logical operations */
> --
> 1.6.0.5
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 02/14] Add various NaN-handling macros
2009-02-03 19:41 ` Aurelien Jarno
@ 2009-02-03 20:19 ` Nathan Froyd
2009-02-04 9:05 ` Aurelien Jarno
0 siblings, 1 reply; 47+ messages in thread
From: Nathan Froyd @ 2009-02-03 20:19 UTC (permalink / raw)
To: Aurelien Jarno; +Cc: qemu-devel
On Tue, Feb 03, 2009 at 08:41:14PM +0100, Aurelien Jarno wrote:
> On Thu, Jan 22, 2009 at 12:44:02PM -0800, Nathan Froyd wrote:
> > These simplify the implementation of the floating-point Altivec
> > instructions and reduce clutter.
> >
> > +#undef DO_HANDLE_NAN
> > +#undef HANDLE_NAN1
> > +#undef HANDLE_NAN2
> > +#undef HANDLE_NAN3
> > #undef VECTOR_FOR_INORDER_I
> > #undef HI_IDX
> > #undef LO_IDX
>
> This is something already handled by the softfloat code. You should use
> set_default_nan_mode(1, &env->vec_status) to get this behavior. This
> could probably done directly in the init code.
I saw the set_default_nan_mode and considered using it. It doesn't give
the same results as the above macros, though. The Altivec specs say
that if a particular input is a SNaN, then the output is the
corresponding QNaN, not the default NaN for the platform. The default
NaN is only used in specific instances. Also, QNaNs propagate through
Altivec operations; using set_default_nan_mode would mean that the
correct propagation no longer occurs.
-Nathan
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 07/14] Add v{add,sub}fp instructions
2009-02-03 19:52 ` Aurelien Jarno
@ 2009-02-03 20:34 ` Nathan Froyd
2009-02-08 22:39 ` Nathan Froyd
1 sibling, 0 replies; 47+ messages in thread
From: Nathan Froyd @ 2009-02-03 20:34 UTC (permalink / raw)
To: Aurelien Jarno; +Cc: qemu-devel
On Tue, Feb 03, 2009 at 08:52:48PM +0100, Aurelien Jarno wrote:
> On Thu, Jan 22, 2009 at 12:44:07PM -0800, Nathan Froyd wrote:
> > +void helper_vsubfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
> > +{
> > + int i;
> > + for (i = 0; i < ARRAY_SIZE(r->f); i++) {
> > + HANDLE_NAN2(r->f[i], a->f[i], b->f[i]) {
> > + if (unlikely(float32_is_infinity(a->f[i]) &&
> > + float32_is_infinity(b->f[i]) &&
> > + float32_is_neg(a->f[i]) == float32_is_neg(b->f[i]))) {
> > + /* Magnitude subtraction of infinities */
> > + r->u32[i] = 0x7fc00000;
>
> I think this case is already handled by the softfloat code.
Ah, hm, I think you may be right. That's what I get for cargo-culting
the code from the existing float helpers. :)
This means I don't have to separate v{add,sub}fp, either. I'll resubmit
this one; I don't think any of the other patches in the series will
conflict.
-Nathan
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 02/14] Add various NaN-handling macros
2009-02-03 20:19 ` Nathan Froyd
@ 2009-02-04 9:05 ` Aurelien Jarno
0 siblings, 0 replies; 47+ messages in thread
From: Aurelien Jarno @ 2009-02-04 9:05 UTC (permalink / raw)
To: qemu-devel
On Tue, Feb 03, 2009 at 12:19:09PM -0800, Nathan Froyd wrote:
> On Tue, Feb 03, 2009 at 08:41:14PM +0100, Aurelien Jarno wrote:
> > On Thu, Jan 22, 2009 at 12:44:02PM -0800, Nathan Froyd wrote:
> > > These simplify the implementation of the floating-point Altivec
> > > instructions and reduce clutter.
> > >
> > > +#undef DO_HANDLE_NAN
> > > +#undef HANDLE_NAN1
> > > +#undef HANDLE_NAN2
> > > +#undef HANDLE_NAN3
> > > #undef VECTOR_FOR_INORDER_I
> > > #undef HI_IDX
> > > #undef LO_IDX
> >
> > This is something already handled by the softfloat code. You should use
> > set_default_nan_mode(1, &env->vec_status) to get this behavior. This
> > could probably done directly in the init code.
>
> I saw the set_default_nan_mode and considered using it. It doesn't give
> the same results as the above macros, though. The Altivec specs say
> that if a particular input is a SNaN, then the output is the
> corresponding QNaN, not the default NaN for the platform. The default
> NaN is only used in specific instances. Also, QNaNs propagate through
> Altivec operations; using set_default_nan_mode would mean that the
> correct propagation no longer occurs.
Ok, I understand now, I have applied the patch. Thanks.
Aurelien
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 06/14] Add v{max,min}fp instructions
2009-02-03 19:51 ` Aurelien Jarno
@ 2009-02-04 9:06 ` Aurelien Jarno
2009-02-08 22:38 ` Nathan Froyd
0 siblings, 1 reply; 47+ messages in thread
From: Aurelien Jarno @ 2009-02-04 9:06 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
On Tue, Feb 03, 2009 at 08:51:13PM +0100, Aurelien Jarno wrote:
> On Thu, Jan 22, 2009 at 12:44:06PM -0800, Nathan Froyd wrote:
> >
> > Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> > ---
> > target-ppc/helper.h | 2 ++
> > target-ppc/op_helper.c | 19 +++++++++++++++++++
> > target-ppc/translate.c | 2 ++
> > 3 files changed, 23 insertions(+), 0 deletions(-)
> >
> > diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> > index 8c04ba7..ebdeabe 100644
> > --- a/target-ppc/helper.h
> > +++ b/target-ppc/helper.h
> > @@ -232,6 +232,8 @@ DEF_HELPER_3(vsum2sws, void, avr, avr, avr)
> > DEF_HELPER_3(vsum4sbs, void, avr, avr, avr)
> > DEF_HELPER_3(vsum4shs, void, avr, avr, avr)
> > DEF_HELPER_3(vsum4ubs, void, avr, avr, avr)
> > +DEF_HELPER_3(vmaxfp, void, avr, avr, avr)
> > +DEF_HELPER_3(vminfp, void, avr, avr, avr)
> >
> > DEF_HELPER_1(efscfsi, i32, i32)
> > DEF_HELPER_1(efscfui, i32, i32)
> > diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> > index 107f977..717bbd4 100644
> > --- a/target-ppc/op_helper.c
> > +++ b/target-ppc/op_helper.c
> > @@ -2252,6 +2252,25 @@ VMINMAX(uw, u32)
> > #undef VMINMAX_DO
> > #undef VMINMAX
> >
> > +#define VMINMAXFP(suffix, relation) \
> > + void helper_v##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> > + { \
> > + int i; \
> > + for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
> > + HANDLE_NAN2(r->f[i], a->f[i], b->f[i]) { \
> > + int rel = float32_compare_quiet(a->f[i], b->f[i], &env->vec_status); \
>
> Given that we only care about lower / greater, I wonder if it would be
> better to use float32_lt_quiet and reversing the arguments.
>
> > + if (rel == relation) { \
> > + r->f[i] = a->f[i]; \
> > + } else { \
> > + r->f[i] = b->f[i]; \
> > + } \
> > + } \
> > + } \
> > + }
> > +VMINMAXFP(minfp, float_relation_less)
> > +VMINMAXFP(maxfp, float_relation_greater)
> > +#undef VMINMAXFP
> > +
> > void helper_vmladduhm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> > {
> > int i;
> > diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> > index 19abec1..35693e0 100644
> > --- a/target-ppc/translate.c
> > +++ b/target-ppc/translate.c
> > @@ -6395,6 +6395,8 @@ GEN_VXFORM(vsum4sbs, 4, 28);
> > GEN_VXFORM(vsum4shs, 4, 25);
> > GEN_VXFORM(vsum2sws, 4, 26);
> > GEN_VXFORM(vsumsws, 4, 30);
> > +GEN_VXFORM(vmaxfp, 5, 10);
> > +GEN_VXFORM(vminfp, 5, 11);
Note also that those values are wrong. The correct values are 0x10 and
0x11.
> >
> > #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
> > GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
> > --
> > 1.6.0.5
> >
> >
> >
> >
>
> --
> Aurelien Jarno GPG: 1024D/F1BCDB73
> aurelien@aurel32.net http://www.aurel32.net
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 08/14] Add vmaddfp and vnmsubfp instructions
2009-01-22 20:44 ` [Qemu-devel] [PATCH 08/14] Add vmaddfp and vnmsubfp instructions Nathan Froyd
@ 2009-02-04 10:39 ` Aurelien Jarno
2009-02-08 22:39 ` Nathan Froyd
0 siblings, 1 reply; 47+ messages in thread
From: Aurelien Jarno @ 2009-02-04 10:39 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
On Thu, Jan 22, 2009 at 12:44:08PM -0800, Nathan Froyd wrote:
> Do the computation in higher precision and check for invalid operation
> conditions.
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/helper.h | 2 +
> target-ppc/op_helper.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++
> target-ppc/translate.c | 1 +
> 3 files changed, 57 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index a5d1972..6f5d6a6 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -236,6 +236,8 @@ DEF_HELPER_3(vaddfp, void, avr, avr, avr)
> DEF_HELPER_3(vsubfp, void, avr, avr, avr)
> DEF_HELPER_3(vmaxfp, void, avr, avr, avr)
> DEF_HELPER_3(vminfp, void, avr, avr, avr)
> +DEF_HELPER_4(vmaddfp, void, avr, avr, avr, avr)
> +DEF_HELPER_4(vnmsubfp, void, avr, avr, avr, avr)
>
> DEF_HELPER_1(efscfsi, i32, i32)
> DEF_HELPER_1(efscfui, i32, i32)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index d952113..532a08a 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2223,6 +2223,29 @@ VCMP(gtsw, >, s32)
> #undef VCMP_DO
> #undef VCMP
>
> +void helper_vmaddfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> +{
> + int i;
> + for (i = 0; i < ARRAY_SIZE(r->f); i++) {
> + HANDLE_NAN3(r->f[i], a->f[i], b->f[i], c->f[i]) {
> + /* Need to do the computation in higher precision and round
> + * once at the end. */
> + float64 af, cf;
> + af = float32_to_float64(a->f[i], &env->vec_status);
> + cf = float32_to_float64(c->f[i], &env->vec_status);
> + if ((float64_is_infinity(af) && float64_is_zero(cf)) ||
> + (float64_is_zero(af) && float64_is_infinity(cf))) {
> + r->u32[i] = 0x7fc00000;
> + } else {
> + float64 t = float64_mul(af, cf, &env->vec_status);
> + float64 bf = float32_to_float64(b->f[i], &env->vec_status);
> + t = float64_add(t, bf, &env->vec_status);
> + r->f[i] = float64_to_float32(t, &env->vec_status);
> + }
> + }
> + }
> +}
The same way as for v{add,sub} I think the NaN part is already handled
by the softfloat code.
> +
> void helper_vmhaddshs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> {
> int sat = 0;
> @@ -2460,6 +2483,37 @@ VMUL(uh, u16, u32)
> #undef VMUL_DO
> #undef VMUL
>
> +void helper_vnmsubfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> +{
> + int i;
> + for (i = 0; i < ARRAY_SIZE(r->f); i++) {
> + HANDLE_NAN3(r->f[i], a->f[i], b->f[i], c->f[i]) {
> + /* Need to do the computation is higher precision and round
> + * once at the end. */
> + float64 af, cf;
> + af = float32_to_float64(a->f[i], &env->vec_status);
> + cf = float32_to_float64(c->f[i], &env->vec_status);
> + if ((float64_is_infinity(af) && float64_is_zero(cf)) ||
> + (float64_is_zero(af) && float64_is_infinity(cf))) {
> + r->u32[i] = 0x7fc00000;
> + } else {
> + float64 t = float64_mul(af, cf, &env->vec_status);
> + float64 bf = float32_to_float64(b->f[i], &env->vec_status);
> + if (unlikely(float64_is_infinity(t) &&
> + float64_is_infinity(bf) &&
> + float64_is_neg(t) == float64_is_neg(bf))) {
> + /* Magnitude subtraction of infinities */
> + r->u32[i] = 0x7fc00000;
> + } else {
> + t = float64_sub(t, bf, &env->vec_status);
> + t = float64_chs(t);
> + r->f[i] = float64_to_float32(t, &env->vec_status);
> + }
> + }
> + }
> + }
> +}
> +
Same here.
> void helper_vperm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> {
> ppc_avr_t result;
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 6ff46e0..8b67333 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6577,6 +6577,7 @@ GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
> GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
> GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
> GEN_VAFORM_PAIRED(vsel, vperm, 21)
> +GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
>
> /*** SPE extension ***/
> /* Register moves */
> --
> 1.6.0.5
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 10/14] Add vrfi{m,n,p,z} instructions
2009-01-22 20:44 ` [Qemu-devel] [PATCH 10/14] Add vrfi{m,n,p,z} instructions Nathan Froyd
@ 2009-02-04 13:53 ` Aurelien Jarno
0 siblings, 0 replies; 47+ messages in thread
From: Aurelien Jarno @ 2009-02-04 13:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
On Thu, Jan 22, 2009 at 12:44:10PM -0800, Nathan Froyd wrote:
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
Thanks, applied.
> target-ppc/helper.h | 4 ++++
> target-ppc/op_helper.c | 18 ++++++++++++++++++
> target-ppc/translate.c | 4 ++++
> 3 files changed, 26 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index ff4b0db..3c2756e 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -244,6 +244,10 @@ DEF_HELPER_3(vaddfp, void, avr, avr, avr)
> DEF_HELPER_3(vsubfp, void, avr, avr, avr)
> DEF_HELPER_3(vmaxfp, void, avr, avr, avr)
> DEF_HELPER_3(vminfp, void, avr, avr, avr)
> +DEF_HELPER_2(vrfim, void, avr, avr)
> +DEF_HELPER_2(vrfin, void, avr, avr)
> +DEF_HELPER_2(vrfip, void, avr, avr)
> +DEF_HELPER_2(vrfiz, void, avr, avr)
> DEF_HELPER_4(vmaddfp, void, avr, avr, avr, avr)
> DEF_HELPER_4(vnmsubfp, void, avr, avr, avr, avr)
>
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index 4b62735..cd35868 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2658,6 +2658,24 @@ VPK(uwum, u32, u16, I, 0)
> #undef VPK
> #undef PKBIG
>
> +#define VRFI(suffix, rounding) \
> + void helper_vrfi##suffix (ppc_avr_t *r, ppc_avr_t *b) \
> + { \
> + int i; \
> + float_status s = env->vec_status; \
> + set_float_rounding_mode(rounding, &s); \
> + for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
> + HANDLE_NAN1(r->f[i], b->f[i]) { \
> + r->f[i] = float32_round_to_int (b->f[i], &s); \
> + } \
> + } \
> + }
> +VRFI(n, float_round_nearest_even)
> +VRFI(m, float_round_down)
> +VRFI(p, float_round_up)
> +VRFI(z, float_round_to_zero)
> +#undef VRFI
> +
> #define VROTATE(suffix, element) \
> void helper_vrl##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> { \
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 312cbcb..2c111af 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6476,6 +6476,10 @@ GEN_VXFORM_NOA(vupklsb, 7, 10);
> GEN_VXFORM_NOA(vupklsh, 7, 11);
> GEN_VXFORM_NOA(vupkhpx, 7, 13);
> GEN_VXFORM_NOA(vupklpx, 7, 15);
> +GEN_VXFORM_NOA(vrfim, 5, 8);
> +GEN_VXFORM_NOA(vrfin, 5, 9);
> +GEN_VXFORM_NOA(vrfip, 5, 10);
> +GEN_VXFORM_NOA(vrfiz, 5, 11);
>
> #define GEN_VXFORM_SIMM(name, opc2, opc3) \
> GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
> --
> 1.6.0.5
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 11/14] Add vcf{u,s}x instructions
2009-01-22 20:44 ` [Qemu-devel] [PATCH 11/14] Add vcf{u,s}x instructions Nathan Froyd
@ 2009-02-04 13:54 ` Aurelien Jarno
0 siblings, 0 replies; 47+ messages in thread
From: Aurelien Jarno @ 2009-02-04 13:54 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
On Thu, Jan 22, 2009 at 12:44:11PM -0800, Nathan Froyd wrote:
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Thanks, applied.
> ---
> target-ppc/helper.h | 2 ++
> target-ppc/op_helper.c | 13 +++++++++++++
> target-ppc/translate.c | 2 ++
> 3 files changed, 17 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 3c2756e..6e25d94 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -250,6 +250,8 @@ DEF_HELPER_2(vrfip, void, avr, avr)
> DEF_HELPER_2(vrfiz, void, avr, avr)
> DEF_HELPER_4(vmaddfp, void, avr, avr, avr, avr)
> DEF_HELPER_4(vnmsubfp, void, avr, avr, avr, avr)
> +DEF_HELPER_3(vcfux, void, avr, avr, i32)
> +DEF_HELPER_3(vcfsx, void, avr, avr, i32)
>
> DEF_HELPER_1(efscfsi, i32, i32)
> DEF_HELPER_1(efscfui, i32, i32)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index cd35868..32ea54f 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2187,6 +2187,19 @@ VAVG(w, s32, int64_t, u32, uint64_t)
> #undef VAVG_DO
> #undef VAVG
>
> +#define VCF(suffix, cvt, element) \
> + void helper_vcf##suffix (ppc_avr_t *r, ppc_avr_t *b, uint32_t uim) \
> + { \
> + int i; \
> + for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
> + float32 t = cvt(b->element[i], &env->vec_status); \
> + r->f[i] = float32_scalbn (t, -uim, &env->vec_status); \
> + } \
> + }
> +VCF(ux, uint32_to_float32, u32)
> +VCF(sx, int32_to_float32, s32)
> +#undef VCF
> +
> #define VCMP_DO(suffix, compare, element, record) \
> void helper_vcmp##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> { \
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 2c111af..e0cbf45 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6518,6 +6518,8 @@ GEN_VXFORM_NOA(vrfiz, 5, 11);
> GEN_VXFORM_UIMM(vspltb, 6, 8);
> GEN_VXFORM_UIMM(vsplth, 6, 9);
> GEN_VXFORM_UIMM(vspltw, 6, 10);
> +GEN_VXFORM_UIMM(vcfux, 5, 12);
> +GEN_VXFORM_UIMM(vcfsx, 5, 13);
>
> GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
> {
> --
> 1.6.0.5
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 13/14] Add vrefp instruction
2009-01-22 20:44 ` [Qemu-devel] [PATCH 13/14] Add vrefp instruction Nathan Froyd
@ 2009-02-04 13:56 ` Aurelien Jarno
2009-02-08 22:44 ` Nathan Froyd
0 siblings, 1 reply; 47+ messages in thread
From: Aurelien Jarno @ 2009-02-04 13:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
On Thu, Jan 22, 2009 at 12:44:13PM -0800, Nathan Froyd wrote:
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/helper.h | 1 +
> target-ppc/op_helper.c | 27 +++++++++++++++++++++++++++
> target-ppc/translate.c | 1 +
> 3 files changed, 29 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index a463787..516cee0 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -244,6 +244,7 @@ DEF_HELPER_3(vaddfp, void, avr, avr, avr)
> DEF_HELPER_3(vsubfp, void, avr, avr, avr)
> DEF_HELPER_3(vmaxfp, void, avr, avr, avr)
> DEF_HELPER_3(vminfp, void, avr, avr, avr)
> +DEF_HELPER_2(vrefp, void, avr, avr)
> DEF_HELPER_2(vrfim, void, avr, avr)
> DEF_HELPER_2(vrfin, void, avr, avr)
> DEF_HELPER_2(vrfip, void, avr, avr)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index e1022ab..8055e1a 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2696,6 +2696,33 @@ VPK(uwum, u32, u16, I, 0)
> #undef VPK
> #undef PKBIG
>
> +void helper_vrefp (ppc_avr_t *r, ppc_avr_t *b)
> +{
> + int i;
> + for (i = 0; i < ARRAY_SIZE(r->f); i++) {
> + HANDLE_NAN1(r->f[i], b->f[i]) {
> + if (float32_is_infinity(b->f[i])) {
> + if (float32_is_neg(b->f[i])) {
> + r->f[i] = float32_chs(float32_zero);
> + } else {
> + r->f[i] = float32_zero;
> + }
> + } else if (float32_is_zero(b->f[i])) {
> + if (float32_is_neg(b->f[i])) {
> + /* Negative infinity */
> + r->u32[i] = 0xff800000;
> + } else {
> + /* Positive infinity */
> + r->u32[i] = 0x7f800000;
> + }
> + } else {
All those cases should be already handled by the softfloat code.
> + float32 one = int32_to_float32(1, &env->vec_status);
I don't really like doing a live conversion each time the conversion is
used. Please use the new float32_one instead.
> + r->f[i] = float32_div(one, b->f[i], &env->vec_status);
> + }
> + }
> + }
> +}
> +
> #define VRFI(suffix, rounding) \
> void helper_vrfi##suffix (ppc_avr_t *r, ppc_avr_t *b) \
> { \
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 81011a2..01a4f11 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6476,6 +6476,7 @@ GEN_VXFORM_NOA(vupklsb, 7, 10);
> GEN_VXFORM_NOA(vupklsh, 7, 11);
> GEN_VXFORM_NOA(vupkhpx, 7, 13);
> GEN_VXFORM_NOA(vupklpx, 7, 15);
> +GEN_VXFORM_NOA(vrefp, 5, 4);
> GEN_VXFORM_NOA(vrfim, 5, 8);
> GEN_VXFORM_NOA(vrfin, 5, 9);
> GEN_VXFORM_NOA(vrfip, 5, 10);
> --
> 1.6.0.5
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 14/14] Add vrsqrtefp instruction
2009-01-22 20:44 ` [Qemu-devel] [PATCH 14/14] Add vrsqrtefp instruction Nathan Froyd
@ 2009-02-04 13:56 ` Aurelien Jarno
2009-02-08 22:44 ` Nathan Froyd
0 siblings, 1 reply; 47+ messages in thread
From: Aurelien Jarno @ 2009-02-04 13:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
On Thu, Jan 22, 2009 at 12:44:14PM -0800, Nathan Froyd wrote:
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/helper.h | 1 +
> target-ppc/op_helper.c | 28 ++++++++++++++++++++++++++++
> target-ppc/translate.c | 1 +
> 3 files changed, 30 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 516cee0..179f077 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -245,6 +245,7 @@ DEF_HELPER_3(vsubfp, void, avr, avr, avr)
> DEF_HELPER_3(vmaxfp, void, avr, avr, avr)
> DEF_HELPER_3(vminfp, void, avr, avr, avr)
> DEF_HELPER_2(vrefp, void, avr, avr)
> +DEF_HELPER_2(vrsqrtefp, void, avr, avr)
> DEF_HELPER_2(vrfim, void, avr, avr)
> DEF_HELPER_2(vrfin, void, avr, avr)
> DEF_HELPER_2(vrfip, void, avr, avr)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index 8055e1a..4ef0b1c 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2756,6 +2756,34 @@ VROTATE(h, u16)
> VROTATE(w, u32)
> #undef VROTATE
>
> +void helper_vrsqrtefp (ppc_avr_t *r, ppc_avr_t *b)
> +{
> + int i;
> + for (i = 0; i < ARRAY_SIZE(r->f); i++) {
> + HANDLE_NAN1(r->f[i], b->f[i]) {
> + if (float32_is_zero(b->f[i])) {
> + if (float32_is_neg(b->f[i])) {
> + /* Negative infinity */
> + r->u32[i] = 0xff800000;
> + } else {
> + /* Positive infinity */
> + r->u32[i] = 0x7f800000;
> + }
> + } else if (float32_is_neg(b->f[i])) {
> + /* Canonical QNaN */
> + r->u32[i] = 0x7fc00000;
> + } else if (float32_is_infinity(b->f[i])) {
> + /* Negative infinity handled earlier */
> + r->f[i] = float32_zero;
> + } else {
> + float32 one = int32_to_float32(1, &env->vec_status);
> + float32 t = float32_sqrt(b->f[i], &env->vec_status);
> + r->f[i] = float32_div(one, t, &env->vec_status);
The same comments as on the vrefp patch applies here.
> + }
> + }
> + }
> +}
> +
> void helper_vsel (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> {
> r->u64[0] = (a->u64[0] & ~c->u64[0]) | (b->u64[0] & c->u64[0]);
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 01a4f11..1c44c59 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6477,6 +6477,7 @@ GEN_VXFORM_NOA(vupklsh, 7, 11);
> GEN_VXFORM_NOA(vupkhpx, 7, 13);
> GEN_VXFORM_NOA(vupklpx, 7, 15);
> GEN_VXFORM_NOA(vrefp, 5, 4);
> +GEN_VXFORM_NOA(vrsqrtefp, 5, 5);
> GEN_VXFORM_NOA(vrfim, 5, 8);
> GEN_VXFORM_NOA(vrfin, 5, 9);
> GEN_VXFORM_NOA(vrfip, 5, 10);
> --
> 1.6.0.5
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 09/14] Add vcmp{eq,ge,gt,b}fp{,.} instructions
2009-01-22 20:44 ` [Qemu-devel] [PATCH 09/14] Add vcmp{eq,ge,gt,b}fp{,.} instructions Nathan Froyd
@ 2009-02-04 14:12 ` Aurelien Jarno
2009-02-08 22:40 ` [Qemu-devel] [PATCH 09/14] Add vcmp{eq, ge, gt, b}fp{, .} instructions Nathan Froyd
0 siblings, 1 reply; 47+ messages in thread
From: Aurelien Jarno @ 2009-02-04 14:12 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
On Thu, Jan 22, 2009 at 12:44:09PM -0800, Nathan Froyd wrote:
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/helper.h | 8 +++++
> target-ppc/op_helper.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++++
> target-ppc/translate.c | 4 +++
> 3 files changed, 80 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 6f5d6a6..ff4b0db 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -132,6 +132,10 @@ DEF_HELPER_3(vcmpgtuw, void, avr, avr, avr)
> DEF_HELPER_3(vcmpgtsb, void, avr, avr, avr)
> DEF_HELPER_3(vcmpgtsh, void, avr, avr, avr)
> DEF_HELPER_3(vcmpgtsw, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpeqfp, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpgefp, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpgtfp, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpbfp, void, avr, avr, avr)
> DEF_HELPER_3(vcmpequb_dot, void, avr, avr, avr)
> DEF_HELPER_3(vcmpequh_dot, void, avr, avr, avr)
> DEF_HELPER_3(vcmpequw_dot, void, avr, avr, avr)
> @@ -141,6 +145,10 @@ DEF_HELPER_3(vcmpgtuw_dot, void, avr, avr, avr)
> DEF_HELPER_3(vcmpgtsb_dot, void, avr, avr, avr)
> DEF_HELPER_3(vcmpgtsh_dot, void, avr, avr, avr)
> DEF_HELPER_3(vcmpgtsw_dot, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpeqfp_dot, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpgefp_dot, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpgtfp_dot, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpbfp_dot, void, avr, avr, avr)
> DEF_HELPER_3(vmrglb, void, avr, avr, avr)
> DEF_HELPER_3(vmrglh, void, avr, avr, avr)
> DEF_HELPER_3(vmrglw, void, avr, avr, avr)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index 532a08a..4b62735 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2223,6 +2223,74 @@ VCMP(gtsw, >, s32)
> #undef VCMP_DO
> #undef VCMP
>
> +#define VCMPFP_DO(suffix, compare, order, record) \
> + void helper_vcmp##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> + { \
> + uint32_t ones = (uint32_t)-1; \
> + uint32_t all = ones; \
> + uint32_t none = 0; \
> + int i; \
> + for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
> + uint32_t result; \
> + int rel = float32_compare_quiet(a->f[i], b->f[i], &env->vec_status); \
> + if (rel == float_relation_unordered) { \
> + result = 0; \
> + } else if (rel compare order) { \
> + result = ones; \
> + } else { \
> + result = 0; \
> + } \
> + r->u32[i] = result; \
> + all &= result; \
> + none |= result; \
> + } \
> + if (record) { \
> + env->crf[6] = ((all != 0) << 3) | ((none == 0) << 1); \
> + } \
> + }
> +#define VCMPFP(suffix, compare, order) \
> + VCMPFP_DO(suffix, compare, order, 0) \
> + VCMPFP_DO(suffix##_dot, compare, order, 1)
> +VCMPFP(eqfp, ==, float_relation_equal)
> +VCMPFP(gefp, !=, float_relation_less)
> +VCMPFP(gtfp, ==, float_relation_greater)
> +#undef VCMPFP_DO
> +#undef VCMPFP
> +
> +static always_inline void vcmpbfp_internal (ppc_avr_t *r, ppc_avr_t *a,
> + ppc_avr_t *b, int record)
> +{
> + int i;
> + int all_in = 0;
> + for (i = 0; i < ARRAY_SIZE(r->f); i++) {
> + int le_rel = float32_compare_quiet(a->f[i], b->f[i], &env->vec_status);
> + if (le_rel == float_relation_unordered) {
> + r->u32[i] = 0xc0000000;
> + /* ALL_IN does not need to be updated here. */
> + } else {
> + float32 bneg = float32_chs(b->f[i]);
> + int ge_rel = float32_compare_quiet(a->f[i], bneg, &env->vec_status);
> + int le = le_rel != float_relation_greater;
> + int ge = ge_rel != float_relation_less;
> + r->u32[i] = ((!le) << 31) | ((!ge) << 30);
> + all_in |= (!le | !ge);
> + }
> + }
> + if (record) {
> + env->crf[6] = (all_in == 0) << 1;
> + }
> +}
> +
> +void helper_vcmpbfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
> +{
> + vcmpbfp_internal(r, a, b, 0);
> +}
> +
> +void helper_vcmpbfp_dot (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
> +{
> + vcmpbfp_internal(r, a, b, 1);
> +}
> +
> void helper_vmaddfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> {
> int i;
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 8b67333..312cbcb 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6430,6 +6430,10 @@ GEN_VXRFORM(vcmpgtsw, 3, 14)
> GEN_VXRFORM(vcmpgtub, 3, 8)
> GEN_VXRFORM(vcmpgtuh, 3, 9)
> GEN_VXRFORM(vcmpgtuw, 3, 10)
> +GEN_VXRFORM(vcmpeqfp, 3, 3)
> +GEN_VXRFORM(vcmpgefp, 3, 7)
> +GEN_VXRFORM(vcmpgtfp, 3, 11)
> +GEN_VXRFORM(vcmpbfp, 3, 3)
This is obviously wrong, as two different instructions can't have the
same opcode. The correct value for vcmpbfp is 15.
> #define GEN_VXFORM_SIMM(name, opc2, opc3) \
> GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
> --
> 1.6.0.5
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 12/14] Add vct{u,s}xs instructions
2009-01-22 20:44 ` [Qemu-devel] [PATCH 12/14] Add vct{u,s}xs instructions Nathan Froyd
@ 2009-02-04 14:46 ` Aurelien Jarno
2009-02-08 22:40 ` Nathan Froyd
0 siblings, 1 reply; 47+ messages in thread
From: Aurelien Jarno @ 2009-02-04 14:46 UTC (permalink / raw)
To: qemu-devel; +Cc: Nathan Froyd
On Thu, Jan 22, 2009 at 12:44:12PM -0800, Nathan Froyd wrote:
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/helper.h | 2 ++
> target-ppc/op_helper.c | 25 +++++++++++++++++++++++++
> target-ppc/translate.c | 2 ++
> 3 files changed, 29 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 6e25d94..a463787 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -252,6 +252,8 @@ DEF_HELPER_4(vmaddfp, void, avr, avr, avr, avr)
> DEF_HELPER_4(vnmsubfp, void, avr, avr, avr, avr)
> DEF_HELPER_3(vcfux, void, avr, avr, i32)
> DEF_HELPER_3(vcfsx, void, avr, avr, i32)
> +DEF_HELPER_3(vctuxs, void, avr, avr, i32)
> +DEF_HELPER_3(vctsxs, void, avr, avr, i32)
>
> DEF_HELPER_1(efscfsi, i32, i32)
> DEF_HELPER_1(efscfui, i32, i32)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index 32ea54f..e1022ab 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2304,6 +2304,31 @@ void helper_vcmpbfp_dot (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
> vcmpbfp_internal(r, a, b, 1);
> }
>
> +#define VCT(suffix, type, floatcvt, satcvt, element) \
> + void helper_vct##suffix (ppc_avr_t *r, ppc_avr_t *b, uint32_t uim) \
> + { \
> + int i; \
> + int sat = 0; \
> + for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
> + if (float32_is_nan(b->f[i]) || \
> + float32_is_signaling_nan(b->f[i])) { \
> + r->element[i] = 0; \
> + } else { \
> + float64 t = float32_to_float64(b->f[i], &env->vec_status); \
> + type j; \
> + t = float64_scalbn(t, uim, &env->vec_status); \
> + j = floatcvt(t, &env->vec_status); \
> + r->element[i] = satcvt(j, &sat); \
> + } \
> + } \
> + if (sat) { \
> + env->vscr |= (1 << VSCR_SAT); \
> + } \
> + }
> +VCT(uxs, uint64_t, float64_to_uint64, cvtuduw, u32)
This doesn't work as a negative value should set VSCR_SAT. The solution
is to use instead:
VCT(uxs, int64_t, float64_to_int64, cvtsduw, u32)
Also the documentation says that the Round toward Zero mode should be
selected for this instruction.
> +VCT(sxs, int64_t, float64_to_int64, cvtsdsw, s32)
> +#undef VCT
> +
> void helper_vmaddfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> {
> int i;
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index e0cbf45..81011a2 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6520,6 +6520,8 @@ GEN_VXFORM_UIMM(vsplth, 6, 9);
> GEN_VXFORM_UIMM(vspltw, 6, 10);
> GEN_VXFORM_UIMM(vcfux, 5, 12);
> GEN_VXFORM_UIMM(vcfsx, 5, 13);
> +GEN_VXFORM_UIMM(vctuxs, 5, 14);
> +GEN_VXFORM_UIMM(vctsxs, 5, 15);
>
> GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
> {
> --
> 1.6.0.5
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 06/14] Add v{max,min}fp instructions
2009-02-04 9:06 ` Aurelien Jarno
@ 2009-02-08 22:38 ` Nathan Froyd
2009-02-09 16:50 ` Aurelien Jarno
0 siblings, 1 reply; 47+ messages in thread
From: Nathan Froyd @ 2009-02-08 22:38 UTC (permalink / raw)
To: qemu-devel
Use float32_lt_quiet instead of an explicit lt/eq/gt/un compare,
since we already handled NaNs earlier.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 2 ++
target-ppc/op_helper.c | 18 ++++++++++++++++++
target-ppc/translate.c | 2 ++
3 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 1c1e878..1c76586 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -232,6 +232,8 @@ DEF_HELPER_3(vsum2sws, void, avr, avr, avr)
DEF_HELPER_3(vsum4sbs, void, avr, avr, avr)
DEF_HELPER_3(vsum4shs, void, avr, avr, avr)
DEF_HELPER_3(vsum4ubs, void, avr, avr, avr)
+DEF_HELPER_3(vmaxfp, void, avr, avr, avr)
+DEF_HELPER_3(vminfp, void, avr, avr, avr)
DEF_HELPER_2(vlogefp, void, avr, avr)
DEF_HELPER_2(vrfim, void, avr, avr)
DEF_HELPER_2(vrfin, void, avr, avr)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 715f86b..674a21d 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2262,6 +2262,24 @@ VMINMAX(uw, u32)
#undef VMINMAX_DO
#undef VMINMAX
+#define VMINMAXFP(suffix, rT, rF) \
+ void helper_v##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+ { \
+ int i; \
+ for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
+ HANDLE_NAN2(r->f[i], a->f[i], b->f[i]) { \
+ if (float32_lt_quiet(a->f[i], b->f[i], &env->vec_status)) { \
+ r->f[i] = rT->f[i]; \
+ } else { \
+ r->f[i] = rF->f[i]; \
+ } \
+ } \
+ } \
+ }
+VMINMAXFP(minfp, a, b)
+VMINMAXFP(maxfp, b, a)
+#undef VMINMAXFP
+
void helper_vmladduhm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
{
int i;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index e829498..1f6386b 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6395,6 +6395,8 @@ GEN_VXFORM(vsum4sbs, 4, 28);
GEN_VXFORM(vsum4shs, 4, 25);
GEN_VXFORM(vsum2sws, 4, 26);
GEN_VXFORM(vsumsws, 4, 30);
+GEN_VXFORM(vmaxfp, 5, 16);
+GEN_VXFORM(vminfp, 5, 17);
#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 07/14] Add v{add,sub}fp instructions
2009-02-03 19:52 ` Aurelien Jarno
2009-02-03 20:34 ` Nathan Froyd
@ 2009-02-08 22:39 ` Nathan Froyd
2009-02-09 16:51 ` Aurelien Jarno
1 sibling, 1 reply; 47+ messages in thread
From: Nathan Froyd @ 2009-02-08 22:39 UTC (permalink / raw)
To: qemu-devel
We don't need to split up vaddfp and vsubfp because the softfloat code
already properly handles magnitude subtraction of infinities.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 2 ++
target-ppc/op_helper.c | 14 ++++++++++++++
target-ppc/translate.c | 2 ++
3 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 1c76586..43d1867 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -232,6 +232,8 @@ DEF_HELPER_3(vsum2sws, void, avr, avr, avr)
DEF_HELPER_3(vsum4sbs, void, avr, avr, avr)
DEF_HELPER_3(vsum4shs, void, avr, avr, avr)
DEF_HELPER_3(vsum4ubs, void, avr, avr, avr)
+DEF_HELPER_3(vaddfp, void, avr, avr, avr)
+DEF_HELPER_3(vsubfp, void, avr, avr, avr)
DEF_HELPER_3(vmaxfp, void, avr, avr, avr)
DEF_HELPER_3(vminfp, void, avr, avr, avr)
DEF_HELPER_2(vlogefp, void, avr, avr)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 674a21d..6cf47a3 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2099,6 +2099,20 @@ VARITH(uwm, u32)
#undef VARITH_DO
#undef VARITH
+#define VARITHFP(suffix, func) \
+ void helper_v##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+ { \
+ int i; \
+ for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
+ HANDLE_NAN2(r->f[i], a->f[i], b->f[i]) { \
+ r->f[i] = func(a->f[i], b->f[i], &env->vec_status); \
+ } \
+ } \
+ }
+VARITHFP(addfp, float32_add)
+VARITHFP(subfp, float32_sub)
+#undef VARITHFP
+
#define VARITHSAT_CASE(type, op, cvt, element) \
{ \
type result = (type)a->element[i] op (type)b->element[i]; \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 1f6386b..af83b19 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6395,6 +6395,8 @@ GEN_VXFORM(vsum4sbs, 4, 28);
GEN_VXFORM(vsum4shs, 4, 25);
GEN_VXFORM(vsum2sws, 4, 26);
GEN_VXFORM(vsumsws, 4, 30);
+GEN_VXFORM(vaddfp, 5, 0);
+GEN_VXFORM(vsubfp, 5, 1);
GEN_VXFORM(vmaxfp, 5, 16);
GEN_VXFORM(vminfp, 5, 17);
--
1.6.0.5
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 08/14] Add vmaddfp and vnmsubfp instructions
2009-02-04 10:39 ` Aurelien Jarno
@ 2009-02-08 22:39 ` Nathan Froyd
2009-02-09 16:51 ` Aurelien Jarno
0 siblings, 1 reply; 47+ messages in thread
From: Nathan Froyd @ 2009-02-08 22:39 UTC (permalink / raw)
To: qemu-devel
Let the softfloat code handle the special cases rather than doing
the work ourselves (e.g. magnitude subtraction of infinities).
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 2 ++
target-ppc/op_helper.c | 37 +++++++++++++++++++++++++++++++++++++
target-ppc/translate.c | 1 +
3 files changed, 40 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 43d1867..af6c839 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -236,6 +236,8 @@ DEF_HELPER_3(vaddfp, void, avr, avr, avr)
DEF_HELPER_3(vsubfp, void, avr, avr, avr)
DEF_HELPER_3(vmaxfp, void, avr, avr, avr)
DEF_HELPER_3(vminfp, void, avr, avr, avr)
+DEF_HELPER_4(vmaddfp, void, avr, avr, avr, avr)
+DEF_HELPER_4(vnmsubfp, void, avr, avr, avr, avr)
DEF_HELPER_2(vlogefp, void, avr, avr)
DEF_HELPER_2(vrfim, void, avr, avr)
DEF_HELPER_2(vrfin, void, avr, avr)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 6cf47a3..f59cd15 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2220,6 +2220,24 @@ VCMP(gtsw, >, s32)
#undef VCMP_DO
#undef VCMP
+void helper_vmaddfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(r->f); i++) {
+ HANDLE_NAN3(r->f[i], a->f[i], b->f[i], c->f[i]) {
+ /* Need to do the computation in higher precision and round
+ * once at the end. */
+ float64 af, bf, cf, t;
+ af = float32_to_float64(a->f[i], &env->vec_status);
+ bf = float32_to_float64(b->f[i], &env->vec_status);
+ cf = float32_to_float64(c->f[i], &env->vec_status);
+ t = float64_mul(af, cf, &env->vec_status);
+ t = float64_add(t, bf, &env->vec_status);
+ r->f[i] = float64_to_float32(t, &env->vec_status);
+ }
+ }
+}
+
void helper_vmhaddshs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
{
int sat = 0;
@@ -2456,6 +2474,25 @@ VMUL(uh, u16, u32)
#undef VMUL_DO
#undef VMUL
+void helper_vnmsubfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(r->f); i++) {
+ HANDLE_NAN3(r->f[i], a->f[i], b->f[i], c->f[i]) {
+ /* Need to do the computation is higher precision and round
+ * once at the end. */
+ float64 af, bf, cf, t;
+ af = float32_to_float64(a->f[i], &env->vec_status);
+ bf = float32_to_float64(b->f[i], &env->vec_status);
+ cf = float32_to_float64(c->f[i], &env->vec_status);
+ t = float64_mul(af, cf, &env->vec_status);
+ t = float64_sub(t, bf, &env->vec_status);
+ t = float64_chs(t);
+ r->f[i] = float64_to_float32(t, &env->vec_status);
+ }
+ }
+}
+
void helper_vperm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
{
ppc_avr_t result;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index af83b19..88426af 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6584,6 +6584,7 @@ GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
GEN_VAFORM_PAIRED(vsel, vperm, 21)
+GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
/*** SPE extension ***/
/* Register moves */
--
1.6.0.5
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 09/14] Add vcmp{eq, ge, gt, b}fp{, .} instructions
2009-02-04 14:12 ` Aurelien Jarno
@ 2009-02-08 22:40 ` Nathan Froyd
2009-02-09 16:51 ` Aurelien Jarno
0 siblings, 1 reply; 47+ messages in thread
From: Nathan Froyd @ 2009-02-08 22:40 UTC (permalink / raw)
To: qemu-devel
Use correct opcode for vcmpbfp{,.}.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 8 +++++
target-ppc/op_helper.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++++
target-ppc/translate.c | 4 +++
3 files changed, 80 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index af6c839..089955b 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -132,6 +132,10 @@ DEF_HELPER_3(vcmpgtuw, void, avr, avr, avr)
DEF_HELPER_3(vcmpgtsb, void, avr, avr, avr)
DEF_HELPER_3(vcmpgtsh, void, avr, avr, avr)
DEF_HELPER_3(vcmpgtsw, void, avr, avr, avr)
+DEF_HELPER_3(vcmpeqfp, void, avr, avr, avr)
+DEF_HELPER_3(vcmpgefp, void, avr, avr, avr)
+DEF_HELPER_3(vcmpgtfp, void, avr, avr, avr)
+DEF_HELPER_3(vcmpbfp, void, avr, avr, avr)
DEF_HELPER_3(vcmpequb_dot, void, avr, avr, avr)
DEF_HELPER_3(vcmpequh_dot, void, avr, avr, avr)
DEF_HELPER_3(vcmpequw_dot, void, avr, avr, avr)
@@ -141,6 +145,10 @@ DEF_HELPER_3(vcmpgtuw_dot, void, avr, avr, avr)
DEF_HELPER_3(vcmpgtsb_dot, void, avr, avr, avr)
DEF_HELPER_3(vcmpgtsh_dot, void, avr, avr, avr)
DEF_HELPER_3(vcmpgtsw_dot, void, avr, avr, avr)
+DEF_HELPER_3(vcmpeqfp_dot, void, avr, avr, avr)
+DEF_HELPER_3(vcmpgefp_dot, void, avr, avr, avr)
+DEF_HELPER_3(vcmpgtfp_dot, void, avr, avr, avr)
+DEF_HELPER_3(vcmpbfp_dot, void, avr, avr, avr)
DEF_HELPER_3(vmrglb, void, avr, avr, avr)
DEF_HELPER_3(vmrglh, void, avr, avr, avr)
DEF_HELPER_3(vmrglw, void, avr, avr, avr)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index f59cd15..d40caf0 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2220,6 +2220,74 @@ VCMP(gtsw, >, s32)
#undef VCMP_DO
#undef VCMP
+#define VCMPFP_DO(suffix, compare, order, record) \
+ void helper_vcmp##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+ { \
+ uint32_t ones = (uint32_t)-1; \
+ uint32_t all = ones; \
+ uint32_t none = 0; \
+ int i; \
+ for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
+ uint32_t result; \
+ int rel = float32_compare_quiet(a->f[i], b->f[i], &env->vec_status); \
+ if (rel == float_relation_unordered) { \
+ result = 0; \
+ } else if (rel compare order) { \
+ result = ones; \
+ } else { \
+ result = 0; \
+ } \
+ r->u32[i] = result; \
+ all &= result; \
+ none |= result; \
+ } \
+ if (record) { \
+ env->crf[6] = ((all != 0) << 3) | ((none == 0) << 1); \
+ } \
+ }
+#define VCMPFP(suffix, compare, order) \
+ VCMPFP_DO(suffix, compare, order, 0) \
+ VCMPFP_DO(suffix##_dot, compare, order, 1)
+VCMPFP(eqfp, ==, float_relation_equal)
+VCMPFP(gefp, !=, float_relation_less)
+VCMPFP(gtfp, ==, float_relation_greater)
+#undef VCMPFP_DO
+#undef VCMPFP
+
+static always_inline void vcmpbfp_internal (ppc_avr_t *r, ppc_avr_t *a,
+ ppc_avr_t *b, int record)
+{
+ int i;
+ int all_in = 0;
+ for (i = 0; i < ARRAY_SIZE(r->f); i++) {
+ int le_rel = float32_compare_quiet(a->f[i], b->f[i], &env->vec_status);
+ if (le_rel == float_relation_unordered) {
+ r->u32[i] = 0xc0000000;
+ /* ALL_IN does not need to be updated here. */
+ } else {
+ float32 bneg = float32_chs(b->f[i]);
+ int ge_rel = float32_compare_quiet(a->f[i], bneg, &env->vec_status);
+ int le = le_rel != float_relation_greater;
+ int ge = ge_rel != float_relation_less;
+ r->u32[i] = ((!le) << 31) | ((!ge) << 30);
+ all_in |= (!le | !ge);
+ }
+ }
+ if (record) {
+ env->crf[6] = (all_in == 0) << 1;
+ }
+}
+
+void helper_vcmpbfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ vcmpbfp_internal(r, a, b, 0);
+}
+
+void helper_vcmpbfp_dot (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ vcmpbfp_internal(r, a, b, 1);
+}
+
void helper_vmaddfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
{
int i;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 88426af..a722f65 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6430,6 +6430,10 @@ GEN_VXRFORM(vcmpgtsw, 3, 14)
GEN_VXRFORM(vcmpgtub, 3, 8)
GEN_VXRFORM(vcmpgtuh, 3, 9)
GEN_VXRFORM(vcmpgtuw, 3, 10)
+GEN_VXRFORM(vcmpeqfp, 3, 3)
+GEN_VXRFORM(vcmpgefp, 3, 7)
+GEN_VXRFORM(vcmpgtfp, 3, 11)
+GEN_VXRFORM(vcmpbfp, 3, 15)
#define GEN_VXFORM_SIMM(name, opc2, opc3) \
GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
--
1.6.0.5
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 12/14] Add vct{u,s}xs instructions
2009-02-04 14:46 ` Aurelien Jarno
@ 2009-02-08 22:40 ` Nathan Froyd
2009-02-09 16:52 ` Aurelien Jarno
0 siblings, 1 reply; 47+ messages in thread
From: Nathan Froyd @ 2009-02-08 22:40 UTC (permalink / raw)
To: qemu-devel
Use round-to-zero mode for conversion, convert to int64_t in all cases,
and properly set VSCR_SAT for negative values in vctuxs.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 2 ++
target-ppc/op_helper.c | 27 +++++++++++++++++++++++++++
target-ppc/translate.c | 2 ++
3 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 089955b..3ee04b2 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -253,6 +253,8 @@ DEF_HELPER_2(vrfip, void, avr, avr)
DEF_HELPER_2(vrfiz, void, avr, avr)
DEF_HELPER_3(vcfux, void, avr, avr, i32)
DEF_HELPER_3(vcfsx, void, avr, avr, i32)
+DEF_HELPER_3(vctuxs, void, avr, avr, i32)
+DEF_HELPER_3(vctsxs, void, avr, avr, i32)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index d40caf0..e4c446d 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2288,6 +2288,33 @@ void helper_vcmpbfp_dot (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
vcmpbfp_internal(r, a, b, 1);
}
+#define VCT(suffix, satcvt, element) \
+ void helper_vct##suffix (ppc_avr_t *r, ppc_avr_t *b, uint32_t uim) \
+ { \
+ int i; \
+ int sat = 0; \
+ float_status s = env->vec_status; \
+ set_float_rounding_mode(float_round_to_zero, &s); \
+ for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
+ if (float32_is_nan(b->f[i]) || \
+ float32_is_signaling_nan(b->f[i])) { \
+ r->element[i] = 0; \
+ } else { \
+ float64 t = float32_to_float64(b->f[i], &s); \
+ int64_t j; \
+ t = float64_scalbn(t, uim, &s); \
+ j = float64_to_int64(t, &s); \
+ r->element[i] = satcvt(j, &sat); \
+ } \
+ } \
+ if (sat) { \
+ env->vscr |= (1 << VSCR_SAT); \
+ } \
+ }
+VCT(uxs, cvtsduw, u32)
+VCT(sxs, cvtsdsw, s32)
+#undef VCT
+
void helper_vmaddfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
{
int i;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index a722f65..4d5b45a 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6521,6 +6521,8 @@ GEN_VXFORM_UIMM(vsplth, 6, 9);
GEN_VXFORM_UIMM(vspltw, 6, 10);
GEN_VXFORM_UIMM(vcfux, 5, 12);
GEN_VXFORM_UIMM(vcfsx, 5, 13);
+GEN_VXFORM_UIMM(vctuxs, 5, 14);
+GEN_VXFORM_UIMM(vctsxs, 5, 15);
GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
{
--
1.6.0.5
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 13/14] Add vrefp instruction
2009-02-04 13:56 ` Aurelien Jarno
@ 2009-02-08 22:44 ` Nathan Froyd
2009-02-09 16:52 ` Aurelien Jarno
0 siblings, 1 reply; 47+ messages in thread
From: Nathan Froyd @ 2009-02-08 22:44 UTC (permalink / raw)
To: qemu-devel
Use float32_one constant to avoid repeated conversions. Let the
softfloat code handle any special cases.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 1 +
target-ppc/op_helper.c | 10 ++++++++++
target-ppc/translate.c | 1 +
3 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 3ee04b2..00a573c 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -244,6 +244,7 @@ DEF_HELPER_3(vaddfp, void, avr, avr, avr)
DEF_HELPER_3(vsubfp, void, avr, avr, avr)
DEF_HELPER_3(vmaxfp, void, avr, avr, avr)
DEF_HELPER_3(vminfp, void, avr, avr, avr)
+DEF_HELPER_2(vrefp, void, avr, avr)
DEF_HELPER_4(vmaddfp, void, avr, avr, avr, avr)
DEF_HELPER_4(vnmsubfp, void, avr, avr, avr, avr)
DEF_HELPER_2(vlogefp, void, avr, avr)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index e4c446d..0e78e23 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2664,6 +2664,16 @@ VPK(uwum, u32, u16, I, 0)
#undef VPK
#undef PKBIG
+void helper_vrefp (ppc_avr_t *r, ppc_avr_t *b)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(r->f); i++) {
+ HANDLE_NAN1(r->f[i], b->f[i]) {
+ r->f[i] = float32_div(float32_one, b->f[i], &env->vec_status);
+ }
+ }
+}
+
#define VRFI(suffix, rounding) \
void helper_vrfi##suffix (ppc_avr_t *r, ppc_avr_t *b) \
{ \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 4d5b45a..46bd177 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6476,6 +6476,7 @@ GEN_VXFORM_NOA(vupklsb, 7, 10);
GEN_VXFORM_NOA(vupklsh, 7, 11);
GEN_VXFORM_NOA(vupkhpx, 7, 13);
GEN_VXFORM_NOA(vupklpx, 7, 15);
+GEN_VXFORM_NOA(vrefp, 5, 4);
GEN_VXFORM_NOA(vlogefp, 5, 7);
GEN_VXFORM_NOA(vrfim, 5, 8);
GEN_VXFORM_NOA(vrfin, 5, 9);
--
1.6.0.5
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 14/14] Add vrsqrtefp instruction
2009-02-04 13:56 ` Aurelien Jarno
@ 2009-02-08 22:44 ` Nathan Froyd
2009-02-09 16:52 ` Aurelien Jarno
0 siblings, 1 reply; 47+ messages in thread
From: Nathan Froyd @ 2009-02-08 22:44 UTC (permalink / raw)
To: qemu-devel
Use float32_one constant to avoid repeated conversions. Let the
softfloat code handle any special cases.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-ppc/helper.h | 1 +
target-ppc/op_helper.c | 11 +++++++++++
target-ppc/translate.c | 1 +
3 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 00a573c..85cdd23 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -245,6 +245,7 @@ DEF_HELPER_3(vsubfp, void, avr, avr, avr)
DEF_HELPER_3(vmaxfp, void, avr, avr, avr)
DEF_HELPER_3(vminfp, void, avr, avr, avr)
DEF_HELPER_2(vrefp, void, avr, avr)
+DEF_HELPER_2(vrsqrtefp, void, avr, avr)
DEF_HELPER_4(vmaddfp, void, avr, avr, avr, avr)
DEF_HELPER_4(vnmsubfp, void, avr, avr, avr, avr)
DEF_HELPER_2(vlogefp, void, avr, avr)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 0e78e23..3afd217 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2707,6 +2707,17 @@ VROTATE(h, u16)
VROTATE(w, u32)
#undef VROTATE
+void helper_vrsqrtefp (ppc_avr_t *r, ppc_avr_t *b)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(r->f); i++) {
+ HANDLE_NAN1(r->f[i], b->f[i]) {
+ float32 t = float32_sqrt(b->f[i], &env->vec_status);
+ r->f[i] = float32_div(float32_one, t, &env->vec_status);
+ }
+ }
+}
+
void helper_vsel (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
{
r->u64[0] = (a->u64[0] & ~c->u64[0]) | (b->u64[0] & c->u64[0]);
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 46bd177..048bb54 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6477,6 +6477,7 @@ GEN_VXFORM_NOA(vupklsh, 7, 11);
GEN_VXFORM_NOA(vupkhpx, 7, 13);
GEN_VXFORM_NOA(vupklpx, 7, 15);
GEN_VXFORM_NOA(vrefp, 5, 4);
+GEN_VXFORM_NOA(vrsqrtefp, 5, 5);
GEN_VXFORM_NOA(vlogefp, 5, 7);
GEN_VXFORM_NOA(vrfim, 5, 8);
GEN_VXFORM_NOA(vrfin, 5, 9);
--
1.6.0.5
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 06/14] Add v{max,min}fp instructions
2009-02-08 22:38 ` Nathan Froyd
@ 2009-02-09 16:50 ` Aurelien Jarno
0 siblings, 0 replies; 47+ messages in thread
From: Aurelien Jarno @ 2009-02-09 16:50 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Sun, Feb 08, 2009 at 02:38:13PM -0800, Nathan Froyd wrote:
> Use float32_lt_quiet instead of an explicit lt/eq/gt/un compare,
> since we already handled NaNs earlier.
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/helper.h | 2 ++
> target-ppc/op_helper.c | 18 ++++++++++++++++++
> target-ppc/translate.c | 2 ++
> 3 files changed, 22 insertions(+), 0 deletions(-)
Thanks applied.
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 1c1e878..1c76586 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -232,6 +232,8 @@ DEF_HELPER_3(vsum2sws, void, avr, avr, avr)
> DEF_HELPER_3(vsum4sbs, void, avr, avr, avr)
> DEF_HELPER_3(vsum4shs, void, avr, avr, avr)
> DEF_HELPER_3(vsum4ubs, void, avr, avr, avr)
> +DEF_HELPER_3(vmaxfp, void, avr, avr, avr)
> +DEF_HELPER_3(vminfp, void, avr, avr, avr)
> DEF_HELPER_2(vlogefp, void, avr, avr)
> DEF_HELPER_2(vrfim, void, avr, avr)
> DEF_HELPER_2(vrfin, void, avr, avr)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index 715f86b..674a21d 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2262,6 +2262,24 @@ VMINMAX(uw, u32)
> #undef VMINMAX_DO
> #undef VMINMAX
>
> +#define VMINMAXFP(suffix, rT, rF) \
> + void helper_v##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> + { \
> + int i; \
> + for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
> + HANDLE_NAN2(r->f[i], a->f[i], b->f[i]) { \
> + if (float32_lt_quiet(a->f[i], b->f[i], &env->vec_status)) { \
> + r->f[i] = rT->f[i]; \
> + } else { \
> + r->f[i] = rF->f[i]; \
> + } \
> + } \
> + } \
> + }
> +VMINMAXFP(minfp, a, b)
> +VMINMAXFP(maxfp, b, a)
> +#undef VMINMAXFP
> +
> void helper_vmladduhm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> {
> int i;
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index e829498..1f6386b 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6395,6 +6395,8 @@ GEN_VXFORM(vsum4sbs, 4, 28);
> GEN_VXFORM(vsum4shs, 4, 25);
> GEN_VXFORM(vsum2sws, 4, 26);
> GEN_VXFORM(vsumsws, 4, 30);
> +GEN_VXFORM(vmaxfp, 5, 16);
> +GEN_VXFORM(vminfp, 5, 17);
>
> #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
> GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
> --
> 1.6.0.5
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 07/14] Add v{add,sub}fp instructions
2009-02-08 22:39 ` Nathan Froyd
@ 2009-02-09 16:51 ` Aurelien Jarno
0 siblings, 0 replies; 47+ messages in thread
From: Aurelien Jarno @ 2009-02-09 16:51 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Sun, Feb 08, 2009 at 02:39:04PM -0800, Nathan Froyd wrote:
> We don't need to split up vaddfp and vsubfp because the softfloat code
> already properly handles magnitude subtraction of infinities.
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/helper.h | 2 ++
> target-ppc/op_helper.c | 14 ++++++++++++++
> target-ppc/translate.c | 2 ++
> 3 files changed, 18 insertions(+), 0 deletions(-)
Thanks, applied.
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 1c76586..43d1867 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -232,6 +232,8 @@ DEF_HELPER_3(vsum2sws, void, avr, avr, avr)
> DEF_HELPER_3(vsum4sbs, void, avr, avr, avr)
> DEF_HELPER_3(vsum4shs, void, avr, avr, avr)
> DEF_HELPER_3(vsum4ubs, void, avr, avr, avr)
> +DEF_HELPER_3(vaddfp, void, avr, avr, avr)
> +DEF_HELPER_3(vsubfp, void, avr, avr, avr)
> DEF_HELPER_3(vmaxfp, void, avr, avr, avr)
> DEF_HELPER_3(vminfp, void, avr, avr, avr)
> DEF_HELPER_2(vlogefp, void, avr, avr)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index 674a21d..6cf47a3 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2099,6 +2099,20 @@ VARITH(uwm, u32)
> #undef VARITH_DO
> #undef VARITH
>
> +#define VARITHFP(suffix, func) \
> + void helper_v##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> + { \
> + int i; \
> + for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
> + HANDLE_NAN2(r->f[i], a->f[i], b->f[i]) { \
> + r->f[i] = func(a->f[i], b->f[i], &env->vec_status); \
> + } \
> + } \
> + }
> +VARITHFP(addfp, float32_add)
> +VARITHFP(subfp, float32_sub)
> +#undef VARITHFP
> +
> #define VARITHSAT_CASE(type, op, cvt, element) \
> { \
> type result = (type)a->element[i] op (type)b->element[i]; \
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 1f6386b..af83b19 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6395,6 +6395,8 @@ GEN_VXFORM(vsum4sbs, 4, 28);
> GEN_VXFORM(vsum4shs, 4, 25);
> GEN_VXFORM(vsum2sws, 4, 26);
> GEN_VXFORM(vsumsws, 4, 30);
> +GEN_VXFORM(vaddfp, 5, 0);
> +GEN_VXFORM(vsubfp, 5, 1);
> GEN_VXFORM(vmaxfp, 5, 16);
> GEN_VXFORM(vminfp, 5, 17);
>
> --
> 1.6.0.5
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 08/14] Add vmaddfp and vnmsubfp instructions
2009-02-08 22:39 ` Nathan Froyd
@ 2009-02-09 16:51 ` Aurelien Jarno
0 siblings, 0 replies; 47+ messages in thread
From: Aurelien Jarno @ 2009-02-09 16:51 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Sun, Feb 08, 2009 at 02:39:34PM -0800, Nathan Froyd wrote:
> Let the softfloat code handle the special cases rather than doing
> the work ourselves (e.g. magnitude subtraction of infinities).
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/helper.h | 2 ++
> target-ppc/op_helper.c | 37 +++++++++++++++++++++++++++++++++++++
> target-ppc/translate.c | 1 +
> 3 files changed, 40 insertions(+), 0 deletions(-)
Thanks, applied.
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 43d1867..af6c839 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -236,6 +236,8 @@ DEF_HELPER_3(vaddfp, void, avr, avr, avr)
> DEF_HELPER_3(vsubfp, void, avr, avr, avr)
> DEF_HELPER_3(vmaxfp, void, avr, avr, avr)
> DEF_HELPER_3(vminfp, void, avr, avr, avr)
> +DEF_HELPER_4(vmaddfp, void, avr, avr, avr, avr)
> +DEF_HELPER_4(vnmsubfp, void, avr, avr, avr, avr)
> DEF_HELPER_2(vlogefp, void, avr, avr)
> DEF_HELPER_2(vrfim, void, avr, avr)
> DEF_HELPER_2(vrfin, void, avr, avr)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index 6cf47a3..f59cd15 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2220,6 +2220,24 @@ VCMP(gtsw, >, s32)
> #undef VCMP_DO
> #undef VCMP
>
> +void helper_vmaddfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> +{
> + int i;
> + for (i = 0; i < ARRAY_SIZE(r->f); i++) {
> + HANDLE_NAN3(r->f[i], a->f[i], b->f[i], c->f[i]) {
> + /* Need to do the computation in higher precision and round
> + * once at the end. */
> + float64 af, bf, cf, t;
> + af = float32_to_float64(a->f[i], &env->vec_status);
> + bf = float32_to_float64(b->f[i], &env->vec_status);
> + cf = float32_to_float64(c->f[i], &env->vec_status);
> + t = float64_mul(af, cf, &env->vec_status);
> + t = float64_add(t, bf, &env->vec_status);
> + r->f[i] = float64_to_float32(t, &env->vec_status);
> + }
> + }
> +}
> +
> void helper_vmhaddshs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> {
> int sat = 0;
> @@ -2456,6 +2474,25 @@ VMUL(uh, u16, u32)
> #undef VMUL_DO
> #undef VMUL
>
> +void helper_vnmsubfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> +{
> + int i;
> + for (i = 0; i < ARRAY_SIZE(r->f); i++) {
> + HANDLE_NAN3(r->f[i], a->f[i], b->f[i], c->f[i]) {
> + /* Need to do the computation is higher precision and round
> + * once at the end. */
> + float64 af, bf, cf, t;
> + af = float32_to_float64(a->f[i], &env->vec_status);
> + bf = float32_to_float64(b->f[i], &env->vec_status);
> + cf = float32_to_float64(c->f[i], &env->vec_status);
> + t = float64_mul(af, cf, &env->vec_status);
> + t = float64_sub(t, bf, &env->vec_status);
> + t = float64_chs(t);
> + r->f[i] = float64_to_float32(t, &env->vec_status);
> + }
> + }
> +}
> +
> void helper_vperm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> {
> ppc_avr_t result;
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index af83b19..88426af 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6584,6 +6584,7 @@ GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
> GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
> GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
> GEN_VAFORM_PAIRED(vsel, vperm, 21)
> +GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
>
> /*** SPE extension ***/
> /* Register moves */
> --
> 1.6.0.5
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 09/14] Add vcmp{eq, ge, gt, b}fp{, .} instructions
2009-02-08 22:40 ` [Qemu-devel] [PATCH 09/14] Add vcmp{eq, ge, gt, b}fp{, .} instructions Nathan Froyd
@ 2009-02-09 16:51 ` Aurelien Jarno
0 siblings, 0 replies; 47+ messages in thread
From: Aurelien Jarno @ 2009-02-09 16:51 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Sun, Feb 08, 2009 at 02:40:03PM -0800, Nathan Froyd wrote:
> Use correct opcode for vcmpbfp{,.}.
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/helper.h | 8 +++++
> target-ppc/op_helper.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++++
> target-ppc/translate.c | 4 +++
> 3 files changed, 80 insertions(+), 0 deletions(-)
Thanks, applied.
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index af6c839..089955b 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -132,6 +132,10 @@ DEF_HELPER_3(vcmpgtuw, void, avr, avr, avr)
> DEF_HELPER_3(vcmpgtsb, void, avr, avr, avr)
> DEF_HELPER_3(vcmpgtsh, void, avr, avr, avr)
> DEF_HELPER_3(vcmpgtsw, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpeqfp, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpgefp, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpgtfp, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpbfp, void, avr, avr, avr)
> DEF_HELPER_3(vcmpequb_dot, void, avr, avr, avr)
> DEF_HELPER_3(vcmpequh_dot, void, avr, avr, avr)
> DEF_HELPER_3(vcmpequw_dot, void, avr, avr, avr)
> @@ -141,6 +145,10 @@ DEF_HELPER_3(vcmpgtuw_dot, void, avr, avr, avr)
> DEF_HELPER_3(vcmpgtsb_dot, void, avr, avr, avr)
> DEF_HELPER_3(vcmpgtsh_dot, void, avr, avr, avr)
> DEF_HELPER_3(vcmpgtsw_dot, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpeqfp_dot, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpgefp_dot, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpgtfp_dot, void, avr, avr, avr)
> +DEF_HELPER_3(vcmpbfp_dot, void, avr, avr, avr)
> DEF_HELPER_3(vmrglb, void, avr, avr, avr)
> DEF_HELPER_3(vmrglh, void, avr, avr, avr)
> DEF_HELPER_3(vmrglw, void, avr, avr, avr)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index f59cd15..d40caf0 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2220,6 +2220,74 @@ VCMP(gtsw, >, s32)
> #undef VCMP_DO
> #undef VCMP
>
> +#define VCMPFP_DO(suffix, compare, order, record) \
> + void helper_vcmp##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> + { \
> + uint32_t ones = (uint32_t)-1; \
> + uint32_t all = ones; \
> + uint32_t none = 0; \
> + int i; \
> + for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
> + uint32_t result; \
> + int rel = float32_compare_quiet(a->f[i], b->f[i], &env->vec_status); \
> + if (rel == float_relation_unordered) { \
> + result = 0; \
> + } else if (rel compare order) { \
> + result = ones; \
> + } else { \
> + result = 0; \
> + } \
> + r->u32[i] = result; \
> + all &= result; \
> + none |= result; \
> + } \
> + if (record) { \
> + env->crf[6] = ((all != 0) << 3) | ((none == 0) << 1); \
> + } \
> + }
> +#define VCMPFP(suffix, compare, order) \
> + VCMPFP_DO(suffix, compare, order, 0) \
> + VCMPFP_DO(suffix##_dot, compare, order, 1)
> +VCMPFP(eqfp, ==, float_relation_equal)
> +VCMPFP(gefp, !=, float_relation_less)
> +VCMPFP(gtfp, ==, float_relation_greater)
> +#undef VCMPFP_DO
> +#undef VCMPFP
> +
> +static always_inline void vcmpbfp_internal (ppc_avr_t *r, ppc_avr_t *a,
> + ppc_avr_t *b, int record)
> +{
> + int i;
> + int all_in = 0;
> + for (i = 0; i < ARRAY_SIZE(r->f); i++) {
> + int le_rel = float32_compare_quiet(a->f[i], b->f[i], &env->vec_status);
> + if (le_rel == float_relation_unordered) {
> + r->u32[i] = 0xc0000000;
> + /* ALL_IN does not need to be updated here. */
> + } else {
> + float32 bneg = float32_chs(b->f[i]);
> + int ge_rel = float32_compare_quiet(a->f[i], bneg, &env->vec_status);
> + int le = le_rel != float_relation_greater;
> + int ge = ge_rel != float_relation_less;
> + r->u32[i] = ((!le) << 31) | ((!ge) << 30);
> + all_in |= (!le | !ge);
> + }
> + }
> + if (record) {
> + env->crf[6] = (all_in == 0) << 1;
> + }
> +}
> +
> +void helper_vcmpbfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
> +{
> + vcmpbfp_internal(r, a, b, 0);
> +}
> +
> +void helper_vcmpbfp_dot (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
> +{
> + vcmpbfp_internal(r, a, b, 1);
> +}
> +
> void helper_vmaddfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> {
> int i;
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 88426af..a722f65 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6430,6 +6430,10 @@ GEN_VXRFORM(vcmpgtsw, 3, 14)
> GEN_VXRFORM(vcmpgtub, 3, 8)
> GEN_VXRFORM(vcmpgtuh, 3, 9)
> GEN_VXRFORM(vcmpgtuw, 3, 10)
> +GEN_VXRFORM(vcmpeqfp, 3, 3)
> +GEN_VXRFORM(vcmpgefp, 3, 7)
> +GEN_VXRFORM(vcmpgtfp, 3, 11)
> +GEN_VXRFORM(vcmpbfp, 3, 15)
>
> #define GEN_VXFORM_SIMM(name, opc2, opc3) \
> GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
> --
> 1.6.0.5
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 12/14] Add vct{u,s}xs instructions
2009-02-08 22:40 ` Nathan Froyd
@ 2009-02-09 16:52 ` Aurelien Jarno
0 siblings, 0 replies; 47+ messages in thread
From: Aurelien Jarno @ 2009-02-09 16:52 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Sun, Feb 08, 2009 at 02:40:33PM -0800, Nathan Froyd wrote:
> Use round-to-zero mode for conversion, convert to int64_t in all cases,
> and properly set VSCR_SAT for negative values in vctuxs.
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/helper.h | 2 ++
> target-ppc/op_helper.c | 27 +++++++++++++++++++++++++++
> target-ppc/translate.c | 2 ++
> 3 files changed, 31 insertions(+), 0 deletions(-)
Thanks, applied.
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 089955b..3ee04b2 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -253,6 +253,8 @@ DEF_HELPER_2(vrfip, void, avr, avr)
> DEF_HELPER_2(vrfiz, void, avr, avr)
> DEF_HELPER_3(vcfux, void, avr, avr, i32)
> DEF_HELPER_3(vcfsx, void, avr, avr, i32)
> +DEF_HELPER_3(vctuxs, void, avr, avr, i32)
> +DEF_HELPER_3(vctsxs, void, avr, avr, i32)
>
> DEF_HELPER_1(efscfsi, i32, i32)
> DEF_HELPER_1(efscfui, i32, i32)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index d40caf0..e4c446d 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2288,6 +2288,33 @@ void helper_vcmpbfp_dot (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
> vcmpbfp_internal(r, a, b, 1);
> }
>
> +#define VCT(suffix, satcvt, element) \
> + void helper_vct##suffix (ppc_avr_t *r, ppc_avr_t *b, uint32_t uim) \
> + { \
> + int i; \
> + int sat = 0; \
> + float_status s = env->vec_status; \
> + set_float_rounding_mode(float_round_to_zero, &s); \
> + for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
> + if (float32_is_nan(b->f[i]) || \
> + float32_is_signaling_nan(b->f[i])) { \
> + r->element[i] = 0; \
> + } else { \
> + float64 t = float32_to_float64(b->f[i], &s); \
> + int64_t j; \
> + t = float64_scalbn(t, uim, &s); \
> + j = float64_to_int64(t, &s); \
> + r->element[i] = satcvt(j, &sat); \
> + } \
> + } \
> + if (sat) { \
> + env->vscr |= (1 << VSCR_SAT); \
> + } \
> + }
> +VCT(uxs, cvtsduw, u32)
> +VCT(sxs, cvtsdsw, s32)
> +#undef VCT
> +
> void helper_vmaddfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> {
> int i;
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index a722f65..4d5b45a 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6521,6 +6521,8 @@ GEN_VXFORM_UIMM(vsplth, 6, 9);
> GEN_VXFORM_UIMM(vspltw, 6, 10);
> GEN_VXFORM_UIMM(vcfux, 5, 12);
> GEN_VXFORM_UIMM(vcfsx, 5, 13);
> +GEN_VXFORM_UIMM(vctuxs, 5, 14);
> +GEN_VXFORM_UIMM(vctsxs, 5, 15);
>
> GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
> {
> --
> 1.6.0.5
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 13/14] Add vrefp instruction
2009-02-08 22:44 ` Nathan Froyd
@ 2009-02-09 16:52 ` Aurelien Jarno
0 siblings, 0 replies; 47+ messages in thread
From: Aurelien Jarno @ 2009-02-09 16:52 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Sun, Feb 08, 2009 at 02:44:21PM -0800, Nathan Froyd wrote:
> Use float32_one constant to avoid repeated conversions. Let the
> softfloat code handle any special cases.
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/helper.h | 1 +
> target-ppc/op_helper.c | 10 ++++++++++
> target-ppc/translate.c | 1 +
> 3 files changed, 12 insertions(+), 0 deletions(-)
Thanks, applied.
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 3ee04b2..00a573c 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -244,6 +244,7 @@ DEF_HELPER_3(vaddfp, void, avr, avr, avr)
> DEF_HELPER_3(vsubfp, void, avr, avr, avr)
> DEF_HELPER_3(vmaxfp, void, avr, avr, avr)
> DEF_HELPER_3(vminfp, void, avr, avr, avr)
> +DEF_HELPER_2(vrefp, void, avr, avr)
> DEF_HELPER_4(vmaddfp, void, avr, avr, avr, avr)
> DEF_HELPER_4(vnmsubfp, void, avr, avr, avr, avr)
> DEF_HELPER_2(vlogefp, void, avr, avr)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index e4c446d..0e78e23 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2664,6 +2664,16 @@ VPK(uwum, u32, u16, I, 0)
> #undef VPK
> #undef PKBIG
>
> +void helper_vrefp (ppc_avr_t *r, ppc_avr_t *b)
> +{
> + int i;
> + for (i = 0; i < ARRAY_SIZE(r->f); i++) {
> + HANDLE_NAN1(r->f[i], b->f[i]) {
> + r->f[i] = float32_div(float32_one, b->f[i], &env->vec_status);
> + }
> + }
> +}
> +
> #define VRFI(suffix, rounding) \
> void helper_vrfi##suffix (ppc_avr_t *r, ppc_avr_t *b) \
> { \
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 4d5b45a..46bd177 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6476,6 +6476,7 @@ GEN_VXFORM_NOA(vupklsb, 7, 10);
> GEN_VXFORM_NOA(vupklsh, 7, 11);
> GEN_VXFORM_NOA(vupkhpx, 7, 13);
> GEN_VXFORM_NOA(vupklpx, 7, 15);
> +GEN_VXFORM_NOA(vrefp, 5, 4);
> GEN_VXFORM_NOA(vlogefp, 5, 7);
> GEN_VXFORM_NOA(vrfim, 5, 8);
> GEN_VXFORM_NOA(vrfin, 5, 9);
> --
> 1.6.0.5
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH 14/14] Add vrsqrtefp instruction
2009-02-08 22:44 ` Nathan Froyd
@ 2009-02-09 16:52 ` Aurelien Jarno
0 siblings, 0 replies; 47+ messages in thread
From: Aurelien Jarno @ 2009-02-09 16:52 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Sun, Feb 08, 2009 at 02:44:42PM -0800, Nathan Froyd wrote:
> Use float32_one constant to avoid repeated conversions. Let the
> softfloat code handle any special cases.
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-ppc/helper.h | 1 +
> target-ppc/op_helper.c | 11 +++++++++++
> target-ppc/translate.c | 1 +
> 3 files changed, 13 insertions(+), 0 deletions(-)
Thanks, applied.
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 00a573c..85cdd23 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -245,6 +245,7 @@ DEF_HELPER_3(vsubfp, void, avr, avr, avr)
> DEF_HELPER_3(vmaxfp, void, avr, avr, avr)
> DEF_HELPER_3(vminfp, void, avr, avr, avr)
> DEF_HELPER_2(vrefp, void, avr, avr)
> +DEF_HELPER_2(vrsqrtefp, void, avr, avr)
> DEF_HELPER_4(vmaddfp, void, avr, avr, avr, avr)
> DEF_HELPER_4(vnmsubfp, void, avr, avr, avr, avr)
> DEF_HELPER_2(vlogefp, void, avr, avr)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index 0e78e23..3afd217 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2707,6 +2707,17 @@ VROTATE(h, u16)
> VROTATE(w, u32)
> #undef VROTATE
>
> +void helper_vrsqrtefp (ppc_avr_t *r, ppc_avr_t *b)
> +{
> + int i;
> + for (i = 0; i < ARRAY_SIZE(r->f); i++) {
> + HANDLE_NAN1(r->f[i], b->f[i]) {
> + float32 t = float32_sqrt(b->f[i], &env->vec_status);
> + r->f[i] = float32_div(float32_one, t, &env->vec_status);
> + }
> + }
> +}
> +
> void helper_vsel (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> {
> r->u64[0] = (a->u64[0] & ~c->u64[0]) | (b->u64[0] & c->u64[0]);
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 46bd177..048bb54 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6477,6 +6477,7 @@ GEN_VXFORM_NOA(vupklsh, 7, 11);
> GEN_VXFORM_NOA(vupkhpx, 7, 13);
> GEN_VXFORM_NOA(vupklpx, 7, 15);
> GEN_VXFORM_NOA(vrefp, 5, 4);
> +GEN_VXFORM_NOA(vrsqrtefp, 5, 5);
> GEN_VXFORM_NOA(vlogefp, 5, 7);
> GEN_VXFORM_NOA(vrfim, 5, 8);
> GEN_VXFORM_NOA(vrfin, 5, 9);
> --
> 1.6.0.5
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 47+ messages in thread
end of thread, other threads:[~2009-02-09 16:52 UTC | newest]
Thread overview: 47+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2009-01-22 20:44 [Qemu-devel] [PATCH 00/14] target-ppc: add floating-point AltiVec instructions Nathan Froyd
2009-01-22 20:44 ` [Qemu-devel] [PATCH 01/14] Add f field to ppc_avr_t Nathan Froyd
2009-02-03 19:59 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 02/14] Add various NaN-handling macros Nathan Froyd
2009-02-03 19:41 ` Aurelien Jarno
2009-02-03 20:19 ` Nathan Froyd
2009-02-04 9:05 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 03/14] Rename spe_status to vec_status Nathan Froyd
2009-02-03 19:59 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 04/14] Add calls to initialize VSCR on appropriate machines Nathan Froyd
2009-02-03 19:59 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 05/14] Make mtvscr use a helper Nathan Froyd
2009-02-03 19:59 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 06/14] Add v{max,min}fp instructions Nathan Froyd
2009-02-03 19:51 ` Aurelien Jarno
2009-02-04 9:06 ` Aurelien Jarno
2009-02-08 22:38 ` Nathan Froyd
2009-02-09 16:50 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 07/14] Add v{add,sub}fp instructions Nathan Froyd
2009-02-03 19:52 ` Aurelien Jarno
2009-02-03 20:34 ` Nathan Froyd
2009-02-08 22:39 ` Nathan Froyd
2009-02-09 16:51 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 08/14] Add vmaddfp and vnmsubfp instructions Nathan Froyd
2009-02-04 10:39 ` Aurelien Jarno
2009-02-08 22:39 ` Nathan Froyd
2009-02-09 16:51 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 09/14] Add vcmp{eq,ge,gt,b}fp{,.} instructions Nathan Froyd
2009-02-04 14:12 ` Aurelien Jarno
2009-02-08 22:40 ` [Qemu-devel] [PATCH 09/14] Add vcmp{eq, ge, gt, b}fp{, .} instructions Nathan Froyd
2009-02-09 16:51 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 10/14] Add vrfi{m,n,p,z} instructions Nathan Froyd
2009-02-04 13:53 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 11/14] Add vcf{u,s}x instructions Nathan Froyd
2009-02-04 13:54 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 12/14] Add vct{u,s}xs instructions Nathan Froyd
2009-02-04 14:46 ` Aurelien Jarno
2009-02-08 22:40 ` Nathan Froyd
2009-02-09 16:52 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 13/14] Add vrefp instruction Nathan Froyd
2009-02-04 13:56 ` Aurelien Jarno
2009-02-08 22:44 ` Nathan Froyd
2009-02-09 16:52 ` Aurelien Jarno
2009-01-22 20:44 ` [Qemu-devel] [PATCH 14/14] Add vrsqrtefp instruction Nathan Froyd
2009-02-04 13:56 ` Aurelien Jarno
2009-02-08 22:44 ` Nathan Froyd
2009-02-09 16:52 ` Aurelien Jarno
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