From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LXZNw-0001Ge-79 for qemu-devel@nongnu.org; Thu, 12 Feb 2009 06:05:36 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LXZNu-0001EZ-Ij for qemu-devel@nongnu.org; Thu, 12 Feb 2009 06:05:35 -0500 Received: from [199.232.76.173] (port=59359 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LXZNu-0001EN-AP for qemu-devel@nongnu.org; Thu, 12 Feb 2009 06:05:34 -0500 Received: from mx20.gnu.org ([199.232.41.8]:6781) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LXZNu-0001OQ-3W for qemu-devel@nongnu.org; Thu, 12 Feb 2009 06:05:34 -0500 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LXZNt-0004Ae-0y for qemu-devel@nongnu.org; Thu, 12 Feb 2009 06:05:33 -0500 From: Vladimir Prus Subject: Re: [Qemu-devel] SH: Improve the interrupt controller Date: Thu, 12 Feb 2009 14:05:33 +0300 References: <200812112252.17620.vladimir@codesourcery.com> <200902041640.n14GebTp027464@smtp09.dti.ne.jp> <200902081857.n18IvPqn004534@smtp09.dti.ne.jp> In-Reply-To: <200902081857.n18IvPqn004534@smtp09.dti.ne.jp> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200902121405.34112.vladimir@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: takasi-y@ops.dti.ne.jp Cc: qemu-devel@nongnu.org On Sunday 08 February 2009 21:57:25 takasi-y@ops.dti.ne.jp wrote: > Hi, Vladimir. > > I managed to make the code working. > r2d boot, SCI and CF working, and /proc/interrupts increases. > > Essential points modified are below. > 1. sh_intc_init() caller/callee mismatch. > 2. nobody calls sh_intc_set_irl_priorities() > 3. INTC_MODE_DUAL_SET/CLR swapped > I'm not sure 3 in your patch is on purpose or not. > > Attached patch is a diff against rev#6563. > This is yours + my small fixes, which are.. > - Above three > - sh_intc_set_irl_priorities() has switched to sh_intc_init_irl_priorities(). > - sh_intc_set_irl()'s enable hack removed. > - indent,tab/space,brace changed (to what looks like code around) > - reduce INTC_A7() usage > - some others. Hi Yoshii, I have replaced my original patch with your patch in my patch set, and adjusted sh7785 emulation for your changes. It works, but only after I re-do the INTC_MODE_DUAL_SET/CLR swap form my original patch. I think that's about right. Suppose you set a bit in SET register, the interrupt then should be masked out. Here's the relevant code: case INTC_MODE_DUAL_SET: value = *valuep & ~value; break; This clears the relevant bit in 'value', and then: sh_intc_toggle_mask(desc, enum_ids[k], value & mask, priority, 0); this passes '0' for 'enable' parameter to sh_intc_toggle_mask, like it should. However, unless I miss something, it seems like the value read from a register is actually inverted. When reading from a set register we should get 1 for each masked register, and we seem to get 1 for each enabled register. If you agree with this analysis, I can adjust the read function. But probably, it's best if your combined patch is checked in -- as I've said I get a working sh4a emulation based on your patch, and it's problematic to keep such big patches outside the official tree. - Volodya