From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LZ5cs-00028B-Sd for qemu-devel@nongnu.org; Mon, 16 Feb 2009 10:43:18 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LZ5cr-00027C-8i for qemu-devel@nongnu.org; Mon, 16 Feb 2009 10:43:18 -0500 Received: from [199.232.76.173] (port=45212 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LZ5cq-000275-Uu for qemu-devel@nongnu.org; Mon, 16 Feb 2009 10:43:16 -0500 Received: from mx2.redhat.com ([66.187.237.31]:56075) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LZ5cp-0005mI-Qm for qemu-devel@nongnu.org; Mon, 16 Feb 2009 10:43:16 -0500 Date: Mon, 16 Feb 2009 12:42:31 -0300 From: Marcelo Tosatti Subject: Re: [Qemu-devel] [PATCH] Fix GPE registers read/write handling. Message-ID: <20090216154231.GA5837@amt.cnet> References: <20090212081031.29410.5338.stgit@dhcp-1-237.tlv.redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090212081031.29410.5338.stgit@dhcp-1-237.tlv.redhat.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, Anthony Liguori ACK On Thu, Feb 12, 2009 at 10:10:31AM +0200, Gleb Natapov wrote: > For STS register bit are cleared by writing 1 into it. > > Signed-off-by: Gleb Natapov > --- > > hw/acpi.c | 43 +++++++++++++++++++++++++++++++------------ > 1 files changed, 31 insertions(+), 12 deletions(-) > > diff --git a/hw/acpi.c b/hw/acpi.c > index 630910a..5eac1ad 100644 > --- a/hw/acpi.c > +++ b/hw/acpi.c > @@ -579,22 +579,25 @@ struct pci_status { > static struct gpe_regs gpe; > static struct pci_status pci0_status; > > +static uint32_t gpe_read_val(uint16_t val, uint32_t addr) > +{ > + if (addr & 1) > + return (val >> 8) & 0xff; > + return val & 0xff; > +} > + > static uint32_t gpe_readb(void *opaque, uint32_t addr) > { > uint32_t val = 0; > struct gpe_regs *g = opaque; > switch (addr) { > case GPE_BASE: > - val = g->sts & 0xFF; > - break; > case GPE_BASE + 1: > - val = (g->sts >> 8) & 0xFF; > + val = gpe_read_val(g->sts, addr); > break; > case GPE_BASE + 2: > - val = g->en & 0xFF; > - break; > case GPE_BASE + 3: > - val = (g->en >> 8) & 0xFF; > + val = gpe_read_val(g->en, addr); > break; > default: > break; > @@ -606,21 +609,37 @@ static uint32_t gpe_readb(void *opaque, uint32_t addr) > return val; > } > > +static void gpe_write_val(uint16_t *cur, int addr, uint32_t val) > +{ > + if (addr & 1) > + *cur = (*cur & 0xff) | (val << 8); > + else > + *cur = (*cur & 0xff00) | (val & 0xff); > +} > + > +static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val) > +{ > + uint16_t x1, x0 = val & 0xff; > + int shift = (addr & 1) ? 8 : 0; > + > + x1 = (*cur >> shift) & 0xff; > + > + x1 = x1 & ~x0; > + > + *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift); > +} > + > static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) > { > struct gpe_regs *g = opaque; > switch (addr) { > case GPE_BASE: > - g->sts = (g->sts & ~0xFFFF) | (val & 0xFFFF); > - break; > case GPE_BASE + 1: > - g->sts = (g->sts & 0xFFFF) | (val << 8); > + gpe_reset_val(&g->sts, addr, val); > break; > case GPE_BASE + 2: > - g->en = (g->en & ~0xFFFF) | (val & 0xFFFF); > - break; > case GPE_BASE + 3: > - g->en = (g->en & 0xFFFF) | (val << 8); > + gpe_write_val(&g->en, addr, val); > break; > default: > break; > >