* [Qemu-devel] [PATCH] Fix GPE registers read/write handling.
@ 2009-02-12 8:10 Gleb Natapov
2009-02-16 15:36 ` Anthony Liguori
2009-02-16 15:42 ` Marcelo Tosatti
0 siblings, 2 replies; 3+ messages in thread
From: Gleb Natapov @ 2009-02-12 8:10 UTC (permalink / raw)
To: qemu-devel
For STS register bit are cleared by writing 1 into it.
Signed-off-by: Gleb Natapov <gleb@redhat.com>
---
hw/acpi.c | 43 +++++++++++++++++++++++++++++++------------
1 files changed, 31 insertions(+), 12 deletions(-)
diff --git a/hw/acpi.c b/hw/acpi.c
index 630910a..5eac1ad 100644
--- a/hw/acpi.c
+++ b/hw/acpi.c
@@ -579,22 +579,25 @@ struct pci_status {
static struct gpe_regs gpe;
static struct pci_status pci0_status;
+static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
+{
+ if (addr & 1)
+ return (val >> 8) & 0xff;
+ return val & 0xff;
+}
+
static uint32_t gpe_readb(void *opaque, uint32_t addr)
{
uint32_t val = 0;
struct gpe_regs *g = opaque;
switch (addr) {
case GPE_BASE:
- val = g->sts & 0xFF;
- break;
case GPE_BASE + 1:
- val = (g->sts >> 8) & 0xFF;
+ val = gpe_read_val(g->sts, addr);
break;
case GPE_BASE + 2:
- val = g->en & 0xFF;
- break;
case GPE_BASE + 3:
- val = (g->en >> 8) & 0xFF;
+ val = gpe_read_val(g->en, addr);
break;
default:
break;
@@ -606,21 +609,37 @@ static uint32_t gpe_readb(void *opaque, uint32_t addr)
return val;
}
+static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
+{
+ if (addr & 1)
+ *cur = (*cur & 0xff) | (val << 8);
+ else
+ *cur = (*cur & 0xff00) | (val & 0xff);
+}
+
+static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
+{
+ uint16_t x1, x0 = val & 0xff;
+ int shift = (addr & 1) ? 8 : 0;
+
+ x1 = (*cur >> shift) & 0xff;
+
+ x1 = x1 & ~x0;
+
+ *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
+}
+
static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
{
struct gpe_regs *g = opaque;
switch (addr) {
case GPE_BASE:
- g->sts = (g->sts & ~0xFFFF) | (val & 0xFFFF);
- break;
case GPE_BASE + 1:
- g->sts = (g->sts & 0xFFFF) | (val << 8);
+ gpe_reset_val(&g->sts, addr, val);
break;
case GPE_BASE + 2:
- g->en = (g->en & ~0xFFFF) | (val & 0xFFFF);
- break;
case GPE_BASE + 3:
- g->en = (g->en & 0xFFFF) | (val << 8);
+ gpe_write_val(&g->en, addr, val);
break;
default:
break;
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [Qemu-devel] [PATCH] Fix GPE registers read/write handling.
2009-02-12 8:10 [Qemu-devel] [PATCH] Fix GPE registers read/write handling Gleb Natapov
@ 2009-02-16 15:36 ` Anthony Liguori
2009-02-16 15:42 ` Marcelo Tosatti
1 sibling, 0 replies; 3+ messages in thread
From: Anthony Liguori @ 2009-02-16 15:36 UTC (permalink / raw)
To: qemu-devel
Gleb Natapov wrote:
> For STS register bit are cleared by writing 1 into it.
>
> Signed-off-by: Gleb Natapov <gleb@redhat.com>
>
Applied. Thanks.
Regards,
Anthony Liguori
> ---
>
> hw/acpi.c | 43 +++++++++++++++++++++++++++++++------------
> 1 files changed, 31 insertions(+), 12 deletions(-)
>
> diff --git a/hw/acpi.c b/hw/acpi.c
> index 630910a..5eac1ad 100644
> --- a/hw/acpi.c
> +++ b/hw/acpi.c
> @@ -579,22 +579,25 @@ struct pci_status {
> static struct gpe_regs gpe;
> static struct pci_status pci0_status;
>
> +static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
> +{
> + if (addr & 1)
> + return (val >> 8) & 0xff;
> + return val & 0xff;
> +}
> +
> static uint32_t gpe_readb(void *opaque, uint32_t addr)
> {
> uint32_t val = 0;
> struct gpe_regs *g = opaque;
> switch (addr) {
> case GPE_BASE:
> - val = g->sts & 0xFF;
> - break;
> case GPE_BASE + 1:
> - val = (g->sts >> 8) & 0xFF;
> + val = gpe_read_val(g->sts, addr);
> break;
> case GPE_BASE + 2:
> - val = g->en & 0xFF;
> - break;
> case GPE_BASE + 3:
> - val = (g->en >> 8) & 0xFF;
> + val = gpe_read_val(g->en, addr);
> break;
> default:
> break;
> @@ -606,21 +609,37 @@ static uint32_t gpe_readb(void *opaque, uint32_t addr)
> return val;
> }
>
> +static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
> +{
> + if (addr & 1)
> + *cur = (*cur & 0xff) | (val << 8);
> + else
> + *cur = (*cur & 0xff00) | (val & 0xff);
> +}
> +
> +static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
> +{
> + uint16_t x1, x0 = val & 0xff;
> + int shift = (addr & 1) ? 8 : 0;
> +
> + x1 = (*cur >> shift) & 0xff;
> +
> + x1 = x1 & ~x0;
> +
> + *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
> +}
> +
> static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
> {
> struct gpe_regs *g = opaque;
> switch (addr) {
> case GPE_BASE:
> - g->sts = (g->sts & ~0xFFFF) | (val & 0xFFFF);
> - break;
> case GPE_BASE + 1:
> - g->sts = (g->sts & 0xFFFF) | (val << 8);
> + gpe_reset_val(&g->sts, addr, val);
> break;
> case GPE_BASE + 2:
> - g->en = (g->en & ~0xFFFF) | (val & 0xFFFF);
> - break;
> case GPE_BASE + 3:
> - g->en = (g->en & 0xFFFF) | (val << 8);
> + gpe_write_val(&g->en, addr, val);
> break;
> default:
> break;
>
>
>
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [Qemu-devel] [PATCH] Fix GPE registers read/write handling.
2009-02-12 8:10 [Qemu-devel] [PATCH] Fix GPE registers read/write handling Gleb Natapov
2009-02-16 15:36 ` Anthony Liguori
@ 2009-02-16 15:42 ` Marcelo Tosatti
1 sibling, 0 replies; 3+ messages in thread
From: Marcelo Tosatti @ 2009-02-16 15:42 UTC (permalink / raw)
To: qemu-devel, Anthony Liguori
ACK
On Thu, Feb 12, 2009 at 10:10:31AM +0200, Gleb Natapov wrote:
> For STS register bit are cleared by writing 1 into it.
>
> Signed-off-by: Gleb Natapov <gleb@redhat.com>
> ---
>
> hw/acpi.c | 43 +++++++++++++++++++++++++++++++------------
> 1 files changed, 31 insertions(+), 12 deletions(-)
>
> diff --git a/hw/acpi.c b/hw/acpi.c
> index 630910a..5eac1ad 100644
> --- a/hw/acpi.c
> +++ b/hw/acpi.c
> @@ -579,22 +579,25 @@ struct pci_status {
> static struct gpe_regs gpe;
> static struct pci_status pci0_status;
>
> +static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
> +{
> + if (addr & 1)
> + return (val >> 8) & 0xff;
> + return val & 0xff;
> +}
> +
> static uint32_t gpe_readb(void *opaque, uint32_t addr)
> {
> uint32_t val = 0;
> struct gpe_regs *g = opaque;
> switch (addr) {
> case GPE_BASE:
> - val = g->sts & 0xFF;
> - break;
> case GPE_BASE + 1:
> - val = (g->sts >> 8) & 0xFF;
> + val = gpe_read_val(g->sts, addr);
> break;
> case GPE_BASE + 2:
> - val = g->en & 0xFF;
> - break;
> case GPE_BASE + 3:
> - val = (g->en >> 8) & 0xFF;
> + val = gpe_read_val(g->en, addr);
> break;
> default:
> break;
> @@ -606,21 +609,37 @@ static uint32_t gpe_readb(void *opaque, uint32_t addr)
> return val;
> }
>
> +static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
> +{
> + if (addr & 1)
> + *cur = (*cur & 0xff) | (val << 8);
> + else
> + *cur = (*cur & 0xff00) | (val & 0xff);
> +}
> +
> +static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
> +{
> + uint16_t x1, x0 = val & 0xff;
> + int shift = (addr & 1) ? 8 : 0;
> +
> + x1 = (*cur >> shift) & 0xff;
> +
> + x1 = x1 & ~x0;
> +
> + *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
> +}
> +
> static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
> {
> struct gpe_regs *g = opaque;
> switch (addr) {
> case GPE_BASE:
> - g->sts = (g->sts & ~0xFFFF) | (val & 0xFFFF);
> - break;
> case GPE_BASE + 1:
> - g->sts = (g->sts & 0xFFFF) | (val << 8);
> + gpe_reset_val(&g->sts, addr, val);
> break;
> case GPE_BASE + 2:
> - g->en = (g->en & ~0xFFFF) | (val & 0xFFFF);
> - break;
> case GPE_BASE + 3:
> - g->en = (g->en & 0xFFFF) | (val << 8);
> + gpe_write_val(&g->en, addr, val);
> break;
> default:
> break;
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2009-02-16 15:43 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2009-02-12 8:10 [Qemu-devel] [PATCH] Fix GPE registers read/write handling Gleb Natapov
2009-02-16 15:36 ` Anthony Liguori
2009-02-16 15:42 ` Marcelo Tosatti
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).