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From: Vladimir Prus <vladimir@codesourcery.com>
To: takasi-y@ops.dti.ne.jp
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] SH: Improve the interrupt controller
Date: Thu, 19 Feb 2009 22:57:58 +0300	[thread overview]
Message-ID: <200902192257.58689.vladimir@codesourcery.com> (raw)
In-Reply-To: <200902171832.n1HIWFGd002332@smtp09.dti.ne.jp>

[-- Attachment #1: Type: text/plain, Size: 1073 bytes --]

On Tuesday 17 February 2009 21:32:15 takasi-y@ops.dti.ne.jp wrote:
> Hi, Vladimir.
> 
> Some more fixes added. Would you please test this for your target?
> I would like you to post it if it works for yours.
> 
> I've tested 
>  Head: svn://svn.sv.gnu.org/qemu/trunk@6626
>  + Last patch: http://lists.gnu.org/archive/html/qemu-devel/2009-02/msg00546.html
>  + This patch.

Yoshii,

with these patches, I've got lockup again, so I've debugged deeper. The lockup happens
because the TMU0 source was asserted, but not enabled. On 7785, that source is controlled
using:

	- INT2PRI0 register, which is priority register. In debugger, I see write
	to this register being processed, and bumping enable_count.
	- INT2MSKR register (and it's clear register). It's never written.

On the CPU, INT2MSKR is initialized to all zeros, not masking anything. In QEMU,
we set enable_max to 2 and enable_count to 0. Therefore, after INT2PRI0 is written,
processor allows the interrupt, and QEMU does not. I attach a patch to correct
this -- what do you think?

Thanks,
Volodya


- Volodya

[-- Attachment #2: mask_groups.diff --]
[-- Type: text/x-diff, Size: 1295 bytes --]

diff --git a/hw/sh_intc.c b/hw/sh_intc.c
index 7cd1fad..2369e8b 100644
--- a/hw/sh_intc.c
+++ b/hw/sh_intc.c
@@ -367,6 +367,10 @@ static void sh_intc_register_source(struct intc_desc *desc,
 	    for (k = 0; k < ARRAY_SIZE(mr->enum_ids); k++) {
 		if (mr->enum_ids[k] == source) {
 		    s->enable_max++;
+		    // Account for the fact that mask registers are
+		    // zero by default, and therefore don't mask
+		    // an interrupt by default.
+		    s->enable_count++;
 		    break;
 		}
 	    }
@@ -431,6 +435,7 @@ void sh_intc_register_sources(struct intc_desc *desc,
 
 		child = sh_intc_source(desc, gr->enum_ids[k]);
 		child->enable_max += s->enable_max;
+		child->enable_count += s->enable_count;
 	    }
 
 	    /* Chain sources within each group via source->next_enum_id,
@@ -537,3 +542,18 @@ void sh_intc_init_irl_priorities(struct intc_source *s)
 	s->priority = priority-- *2;
     assert(priority == 0);
 }
+
+void sh_intc_debug_lockup (struct intc_desc *desc)
+{
+  int i;
+  for (i = 0; i < desc->nr_sources; i++) 
+    {
+      struct intc_source *source = desc->sources + i;
+
+      if (source->asserted && !source->pending)
+	{
+	  printf ("source %d (%x) asserted, not pending, e = %d/%d\n",
+		  i, source->vect, source->enable_count, source->enable_max);
+	}
+    }
+}

  reply	other threads:[~2009-02-19 19:57 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2008-12-11 19:52 [Qemu-devel] SH: Improve the interrupt controller Vladimir Prus
2008-12-11 21:16 ` Jean-Christophe PLAGNIOL-VILLARD
2008-12-12  5:48   ` [Qemu-devel] " Vladimir Prus
2008-12-14 16:46 ` [Qemu-devel] " takasi-y
2008-12-14 16:57   ` Vladimir Prus
2009-01-26 13:32     ` Vladimir Prus
2009-01-26 23:51       ` Shin-ichiro KAWASAKI
2009-02-04 16:40       ` takasi-y
2009-02-08 18:57         ` takasi-y
2009-02-12 11:05           ` Vladimir Prus
2009-02-17 18:32             ` takasi-y
2009-02-19 19:57               ` Vladimir Prus [this message]
2009-03-13 17:50                 ` takasi-y
2009-03-13 18:32                   ` Vladimir Prus
2009-03-19 17:17                     ` takasi-y
2009-03-19 17:31                       ` Vladimir Prus
2009-02-20  3:06             ` Jean-Christophe PLAGNIOL-VILLARD
2009-02-20  5:16               ` Vladimir Prus
2009-02-20  5:32                 ` Jean-Christophe PLAGNIOL-VILLARD
2009-02-20  5:58                   ` Vladimir Prus
2009-02-20  5:59                     ` Jean-Christophe PLAGNIOL-VILLARD

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