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From: Paul Brook <paul@codesourcery.com>
Subject: Re: [Qemu-devel] [PATCH 7/7] PPC64: Don't fault at lwsync
Date: Fri, 6 Mar 2009 00:53:46 +0000
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To: qemu-devel@nongnu.org
Cc: blauwirbel@gmail.com, Alexander Graf <alex@csgraf.de>, Alexander Graf <agraf@suse.de>

On Thursday 05 March 2009, Daniel Jacobowitz wrote:
> On Thu, Mar 05, 2009 at 04:44:30PM +0000, Paul Brook wrote:
> > When an MMU exception occurs, qemu figures out the guest location from
> > the location of the MMU access in guest code (see cpu_restore_state). My
> > guess is that this breaks when two guest instructions have the same
> > location. I'm not entirely sure what the correct fix is, or where the bug
> > lies
> > (cpu_restore_state,  gen_intermediate_code_pc, or tcg_gen_code_search_pc)
> > but hopefully this will point you in the right direction.
>
> Automatically pick the second instruction, on the principle that an
> instruction with no opcodes is unlikely to trigger a synchronous
> fault?

Yes, that sounds like the right fix.

Paul