From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LhBLS-0008As-CL for qemu-devel@nongnu.org; Tue, 10 Mar 2009 19:26:46 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LhBLR-0008Ae-M9 for qemu-devel@nongnu.org; Tue, 10 Mar 2009 19:26:45 -0400 Received: from [199.232.76.173] (port=46120 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LhBLR-0008Ab-GE for qemu-devel@nongnu.org; Tue, 10 Mar 2009 19:26:45 -0400 Received: from mx20.gnu.org ([199.232.41.8]:40341) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LhBLQ-0002qN-Qv for qemu-devel@nongnu.org; Tue, 10 Mar 2009 19:26:45 -0400 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LhBLP-0007Q2-Sn for qemu-devel@nongnu.org; Tue, 10 Mar 2009 19:26:44 -0400 From: Paul Brook Subject: Re: [Qemu-devel] [6805] tcg: optimize logical operations Date: Tue, 10 Mar 2009 23:26:40 +0000 References: In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Message-Id: <200903102326.41214.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Aurelien Jarno On Tuesday 10 March 2009, Aurelien Jarno wrote: > =C2=A0static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, in= t64_t > - =C2=A0 =C2=A0tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); > - =C2=A0 =C2=A0tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> = 32); > + =C2=A0 =C2=A0if (TCGV_EQUAL_I64(arg1, arg2)) { This is wrong (and breaks 32-bit hosts). > =C2=A0static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv= _i64 > - =C2=A0 =C2=A0tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg= 2)); > - =C2=A0 =C2=A0tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(= arg2)); > + =C2=A0 =C2=A0if (TCGV_EQUAL_I64(arg1, arg2)) { > =C2=A0static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCG= v_i64 > - =C2=A0 =C2=A0tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(ar= g2)); > - =C2=A0 =C2=A0tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH= (arg2)); > + =C2=A0 =C2=A0if (TCGV_EQUAL_I64(arg1, arg2)) { These are pointless. The 32-bit ops already perform these simplifications. Paul