Re: [Qemu-devel] SH: Improve the interrupt controller

[Vladimir Prus <vladimir@codesourcery.com>]

On Friday 13 March 2009 20:50:22 takasi-y@ops.dti.ne.jp wrote:
> Hi,
>
> > On the CPU, INT2MSKR is initialized to all zeros, not masking anything.
> > In QEMU,
>
> Please read HW manual. According to a SH7785 HW manual(REJ09B0261-0100),
> Initial value of four mask registers are
> {ff000000,ff000000,00000000,ffffffff}. There's no general rule for initial
> value of registers.
> But default = 0 not seems to be a bad idea.
> Attached patch enables to supply initial value, otherwise 0.
>
> Tested for little endian r2d on PC with source below
> svn head: svn://svn.sv.gnu.org/qemu/trunk@6838
> + --append patch : Sun, 8 Mar 2009 03:00:17 +0900 (JST)
> + intc old patch : Mon, 9 Feb 2009 03:57:25 +0900 (JST)
> + intc last patch : Wed, 18 Feb 2009 03:32:15 +0900 (JST)
> + This patch.
>
> BTW, our(mostly "my", sorry) slow conversation seems to upset some people.
> I don't care writing code without your source code, 

Hmm, maybe I am confused but I had an impression that you do have access
to the sh4a qemu -- both binary and source. 

> because my reference
> is always a HW manual. But, it is true that this style of development is
> not efficient nor interesting.

Indeed, mailing patches and revisions back and forth is cumbersome. If the
above set of patches works for you for r2d, then maybe the best approach
is to get them checked in -- and then I'll have a baseline to revise my
patch series against?

I assume that core qemu maintainers are not watching this thread closely.
Do you think you can post the above patches -- either combined, or separately,
for review?

Thanks,
Volodya