* [Qemu-devel] [7042] target-mips: optimize decode_opc()
@ 2009-04-08 21:47 Aurelien Jarno
2009-04-12 20:14 ` Stefan Weil
0 siblings, 1 reply; 3+ messages in thread
From: Aurelien Jarno @ 2009-04-08 21:47 UTC (permalink / raw)
To: qemu-devel
Revision: 7042
http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=7042
Author: aurel32
Date: 2009-04-08 21:47:55 +0000 (Wed, 08 Apr 2009)
Log Message:
-----------
target-mips: optimize decode_opc()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Modified Paths:
--------------
trunk/target-mips/translate.c
Modified: trunk/target-mips/translate.c
===================================================================
--- trunk/target-mips/translate.c 2009-04-08 21:47:44 UTC (rev 7041)
+++ trunk/target-mips/translate.c 2009-04-08 21:47:55 UTC (rev 7042)
@@ -7527,7 +7527,6 @@
case OPC_MOVCI:
check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
- save_cpu_state(ctx, 1);
check_cp1_enabled(ctx);
gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
(ctx->opcode >> 16) & 1);
@@ -7623,28 +7622,33 @@
case OPC_RDHWR:
check_insn(env, ctx, ISA_MIPS32R2);
{
- TCGv t0 = tcg_temp_local_new();
+ TCGv t0 = tcg_temp_new();
switch (rd) {
case 0:
save_cpu_state(ctx, 1);
gen_helper_rdhwr_cpunum(t0);
+ gen_store_gpr(t0, rt);
break;
case 1:
save_cpu_state(ctx, 1);
gen_helper_rdhwr_synci_step(t0);
+ gen_store_gpr(t0, rt);
break;
case 2:
save_cpu_state(ctx, 1);
gen_helper_rdhwr_cc(t0);
+ gen_store_gpr(t0, rt);
break;
case 3:
save_cpu_state(ctx, 1);
gen_helper_rdhwr_ccres(t0);
+ gen_store_gpr(t0, rt);
break;
case 29:
#if defined(CONFIG_USER_ONLY)
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, tls_value));
+ gen_store_gpr(t0, rt);
break;
#else
/* XXX: Some CPUs implement this in hardware.
@@ -7655,15 +7659,14 @@
generate_exception(ctx, EXCP_RI);
break;
}
- gen_store_gpr(t0, rt);
tcg_temp_free(t0);
}
break;
case OPC_FORK:
check_insn(env, ctx, ASE_MT);
{
- TCGv t0 = tcg_temp_local_new();
- TCGv t1 = tcg_temp_local_new();
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
gen_load_gpr(t0, rt);
gen_load_gpr(t1, rs);
@@ -7675,8 +7678,9 @@
case OPC_YIELD:
check_insn(env, ctx, ASE_MT);
{
- TCGv t0 = tcg_temp_local_new();
+ TCGv t0 = tcg_temp_new();
+ save_cpu_state(ctx, 1);
gen_load_gpr(t0, rs);
gen_helper_yield(t0, t0);
gen_store_gpr(t0, rd);
@@ -7748,37 +7752,41 @@
case OPC_MFMC0:
#ifndef CONFIG_USER_ONLY
{
- TCGv t0 = tcg_temp_local_new();
+ TCGv t0 = tcg_temp_new();
op2 = MASK_MFMC0(ctx->opcode);
switch (op2) {
case OPC_DMT:
check_insn(env, ctx, ASE_MT);
gen_helper_dmt(t0, t0);
+ gen_store_gpr(t0, rt);
break;
case OPC_EMT:
check_insn(env, ctx, ASE_MT);
gen_helper_emt(t0, t0);
+ gen_store_gpr(t0, rt);
break;
case OPC_DVPE:
check_insn(env, ctx, ASE_MT);
gen_helper_dvpe(t0, t0);
+ gen_store_gpr(t0, rt);
break;
case OPC_EVPE:
check_insn(env, ctx, ASE_MT);
gen_helper_evpe(t0, t0);
+ gen_store_gpr(t0, rt);
break;
case OPC_DI:
check_insn(env, ctx, ISA_MIPS32R2);
- save_cpu_state(ctx, 1);
gen_helper_di(t0);
+ gen_store_gpr(t0, rt);
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
break;
case OPC_EI:
check_insn(env, ctx, ISA_MIPS32R2);
- save_cpu_state(ctx, 1);
gen_helper_ei(t0);
+ gen_store_gpr(t0, rt);
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
break;
@@ -7787,7 +7795,6 @@
generate_exception(ctx, EXCP_RI);
break;
}
- gen_store_gpr(t0, rt);
tcg_temp_free(t0);
}
#endif /* !CONFIG_USER_ONLY */
@@ -7839,7 +7846,6 @@
case OPC_SWC1:
case OPC_SDC1:
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
- save_cpu_state(ctx, 1);
check_cp1_enabled(ctx);
gen_flt_ldst(ctx, op, rt, rs, imm);
} else {
@@ -7849,7 +7855,6 @@
case OPC_CP1:
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
- save_cpu_state(ctx, 1);
check_cp1_enabled(ctx);
op1 = MASK_CP1(ctx->opcode);
switch (op1) {
@@ -7908,7 +7913,6 @@
case OPC_CP3:
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
- save_cpu_state(ctx, 1);
check_cp1_enabled(ctx);
op1 = MASK_CP3(ctx->opcode);
switch (op1) {
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [7042] target-mips: optimize decode_opc()
2009-04-08 21:47 [Qemu-devel] [7042] target-mips: optimize decode_opc() Aurelien Jarno
@ 2009-04-12 20:14 ` Stefan Weil
2009-04-13 8:53 ` Aurelien Jarno
0 siblings, 1 reply; 3+ messages in thread
From: Stefan Weil @ 2009-04-12 20:14 UTC (permalink / raw)
To: qemu-devel, Aurelien Jarno
Aurelien Jarno schrieb:
> Revision: 7042
> http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=7042
> Author: aurel32
> Date: 2009-04-08 21:47:55 +0000 (Wed, 08 Apr 2009)
> Log Message:
> -----------
> target-mips: optimize decode_opc()
>
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
>
> Modified Paths:
> --------------
> trunk/target-mips/translate.c
>
> Modified: trunk/target-mips/translate.c
> ===================================================================
> --- trunk/target-mips/translate.c 2009-04-08 21:47:44 UTC (rev 7041)
> +++ trunk/target-mips/translate.c 2009-04-08 21:47:55 UTC (rev 7042)
> @@ -7527,7 +7527,6 @@
> case OPC_MOVCI:
> check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
> if (env->CP0_Config1 & (1 << CP0C1_FP)) {
> - save_cpu_state(ctx, 1);
> check_cp1_enabled(ctx);
> gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
> (ctx->opcode >> 16) & 1);
> @@ -7623,28 +7622,33 @@
> case OPC_RDHWR:
> check_insn(env, ctx, ISA_MIPS32R2);
> {
> - TCGv t0 = tcg_temp_local_new();
> + TCGv t0 = tcg_temp_new();
>
> switch (rd) {
> case 0:
> save_cpu_state(ctx, 1);
> gen_helper_rdhwr_cpunum(t0);
> + gen_store_gpr(t0, rt);
> break;
> case 1:
> save_cpu_state(ctx, 1);
> gen_helper_rdhwr_synci_step(t0);
> + gen_store_gpr(t0, rt);
> break;
> case 2:
> save_cpu_state(ctx, 1);
> gen_helper_rdhwr_cc(t0);
> + gen_store_gpr(t0, rt);
> break;
> case 3:
> save_cpu_state(ctx, 1);
> gen_helper_rdhwr_ccres(t0);
> + gen_store_gpr(t0, rt);
> break;
> case 29:
> #if defined(CONFIG_USER_ONLY)
> tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, tls_value));
> + gen_store_gpr(t0, rt);
> break;
> #else
> /* XXX: Some CPUs implement this in hardware.
> @@ -7655,15 +7659,14 @@
> generate_exception(ctx, EXCP_RI);
> break;
> }
> - gen_store_gpr(t0, rt);
> tcg_temp_free(t0);
> }
> break;
> case OPC_FORK:
> check_insn(env, ctx, ASE_MT);
> {
> - TCGv t0 = tcg_temp_local_new();
> - TCGv t1 = tcg_temp_local_new();
> + TCGv t0 = tcg_temp_new();
> + TCGv t1 = tcg_temp_new();
>
> gen_load_gpr(t0, rt);
> gen_load_gpr(t1, rs);
> @@ -7675,8 +7678,9 @@
> case OPC_YIELD:
> check_insn(env, ctx, ASE_MT);
> {
> - TCGv t0 = tcg_temp_local_new();
> + TCGv t0 = tcg_temp_new();
>
> + save_cpu_state(ctx, 1);
> gen_load_gpr(t0, rs);
> gen_helper_yield(t0, t0);
> gen_store_gpr(t0, rd);
> @@ -7748,37 +7752,41 @@
> case OPC_MFMC0:
> #ifndef CONFIG_USER_ONLY
> {
> - TCGv t0 = tcg_temp_local_new();
> + TCGv t0 = tcg_temp_new();
>
> op2 = MASK_MFMC0(ctx->opcode);
> switch (op2) {
> case OPC_DMT:
> check_insn(env, ctx, ASE_MT);
> gen_helper_dmt(t0, t0);
> + gen_store_gpr(t0, rt);
> break;
> case OPC_EMT:
> check_insn(env, ctx, ASE_MT);
> gen_helper_emt(t0, t0);
> + gen_store_gpr(t0, rt);
> break;
> case OPC_DVPE:
> check_insn(env, ctx, ASE_MT);
> gen_helper_dvpe(t0, t0);
> + gen_store_gpr(t0, rt);
> break;
> case OPC_EVPE:
> check_insn(env, ctx, ASE_MT);
> gen_helper_evpe(t0, t0);
> + gen_store_gpr(t0, rt);
> break;
> case OPC_DI:
> check_insn(env, ctx, ISA_MIPS32R2);
> - save_cpu_state(ctx, 1);
save_cpu_state needed?
> gen_helper_di(t0);
> + gen_store_gpr(t0, rt);
> /* Stop translation as we may have switched the execution mode */
> ctx->bstate = BS_STOP;
> break;
> case OPC_EI:
> check_insn(env, ctx, ISA_MIPS32R2);
> - save_cpu_state(ctx, 1);
save_cpu_state needed?
> gen_helper_ei(t0);
> + gen_store_gpr(t0, rt);
> /* Stop translation as we may have switched the execution mode */
> ctx->bstate = BS_STOP;
> break;
> @@ -7787,7 +7795,6 @@
> generate_exception(ctx, EXCP_RI);
> break;
> }
> - gen_store_gpr(t0, rt);
> tcg_temp_free(t0);
> }
> #endif /* !CONFIG_USER_ONLY */
> @@ -7839,7 +7846,6 @@
> case OPC_SWC1:
> case OPC_SDC1:
> if (env->CP0_Config1 & (1 << CP0C1_FP)) {
> - save_cpu_state(ctx, 1);
> check_cp1_enabled(ctx);
> gen_flt_ldst(ctx, op, rt, rs, imm);
> } else {
> @@ -7849,7 +7855,6 @@
>
> case OPC_CP1:
> if (env->CP0_Config1 & (1 << CP0C1_FP)) {
> - save_cpu_state(ctx, 1);
> check_cp1_enabled(ctx);
> op1 = MASK_CP1(ctx->opcode);
> switch (op1) {
> @@ -7908,7 +7913,6 @@
>
> case OPC_CP3:
> if (env->CP0_Config1 & (1 << CP0C1_FP)) {
> - save_cpu_state(ctx, 1);
> check_cp1_enabled(ctx);
> op1 = MASK_CP3(ctx->opcode);
> switch (op1) {
>
This patch breaks Linux boot (fatal kernel error during boot,
wrong kernel mode?). I'm sorry that I cannot give more
details at the moment because I have trouble with
my test hardware.
Tested with QEMU trunk, mips little endian, malta machine.
Re-adding the two removed calls of save_cpu_state (for
OPC_DI, OPC_EI) lets the kernel boot again.
Maybe there is a better fix.
Regards
Stefan
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [7042] target-mips: optimize decode_opc()
2009-04-12 20:14 ` Stefan Weil
@ 2009-04-13 8:53 ` Aurelien Jarno
0 siblings, 0 replies; 3+ messages in thread
From: Aurelien Jarno @ 2009-04-13 8:53 UTC (permalink / raw)
To: Stefan Weil; +Cc: qemu-devel
On Sun, Apr 12, 2009 at 10:14:56PM +0200, Stefan Weil wrote:
> Aurelien Jarno schrieb:
> > Revision: 7042
> > http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=7042
> > Author: aurel32
> > Date: 2009-04-08 21:47:55 +0000 (Wed, 08 Apr 2009)
> > Log Message:
> > -----------
> > target-mips: optimize decode_opc()
> >
> > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
> >
> > Modified Paths:
> > --------------
> > trunk/target-mips/translate.c
> >
> > Modified: trunk/target-mips/translate.c
> > ===================================================================
> > --- trunk/target-mips/translate.c 2009-04-08 21:47:44 UTC (rev 7041)
> > +++ trunk/target-mips/translate.c 2009-04-08 21:47:55 UTC (rev 7042)
> > @@ -7527,7 +7527,6 @@
> > case OPC_MOVCI:
> > check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
> > if (env->CP0_Config1 & (1 << CP0C1_FP)) {
> > - save_cpu_state(ctx, 1);
> > check_cp1_enabled(ctx);
> > gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
> > (ctx->opcode >> 16) & 1);
> > @@ -7623,28 +7622,33 @@
> > case OPC_RDHWR:
> > check_insn(env, ctx, ISA_MIPS32R2);
> > {
> > - TCGv t0 = tcg_temp_local_new();
> > + TCGv t0 = tcg_temp_new();
> >
> > switch (rd) {
> > case 0:
> > save_cpu_state(ctx, 1);
> > gen_helper_rdhwr_cpunum(t0);
> > + gen_store_gpr(t0, rt);
> > break;
> > case 1:
> > save_cpu_state(ctx, 1);
> > gen_helper_rdhwr_synci_step(t0);
> > + gen_store_gpr(t0, rt);
> > break;
> > case 2:
> > save_cpu_state(ctx, 1);
> > gen_helper_rdhwr_cc(t0);
> > + gen_store_gpr(t0, rt);
> > break;
> > case 3:
> > save_cpu_state(ctx, 1);
> > gen_helper_rdhwr_ccres(t0);
> > + gen_store_gpr(t0, rt);
> > break;
> > case 29:
> > #if defined(CONFIG_USER_ONLY)
> > tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, tls_value));
> > + gen_store_gpr(t0, rt);
> > break;
> > #else
> > /* XXX: Some CPUs implement this in hardware.
> > @@ -7655,15 +7659,14 @@
> > generate_exception(ctx, EXCP_RI);
> > break;
> > }
> > - gen_store_gpr(t0, rt);
> > tcg_temp_free(t0);
> > }
> > break;
> > case OPC_FORK:
> > check_insn(env, ctx, ASE_MT);
> > {
> > - TCGv t0 = tcg_temp_local_new();
> > - TCGv t1 = tcg_temp_local_new();
> > + TCGv t0 = tcg_temp_new();
> > + TCGv t1 = tcg_temp_new();
> >
> > gen_load_gpr(t0, rt);
> > gen_load_gpr(t1, rs);
> > @@ -7675,8 +7678,9 @@
> > case OPC_YIELD:
> > check_insn(env, ctx, ASE_MT);
> > {
> > - TCGv t0 = tcg_temp_local_new();
> > + TCGv t0 = tcg_temp_new();
> >
> > + save_cpu_state(ctx, 1);
> > gen_load_gpr(t0, rs);
> > gen_helper_yield(t0, t0);
> > gen_store_gpr(t0, rd);
> > @@ -7748,37 +7752,41 @@
> > case OPC_MFMC0:
> > #ifndef CONFIG_USER_ONLY
> > {
> > - TCGv t0 = tcg_temp_local_new();
> > + TCGv t0 = tcg_temp_new();
> >
> > op2 = MASK_MFMC0(ctx->opcode);
> > switch (op2) {
> > case OPC_DMT:
> > check_insn(env, ctx, ASE_MT);
> > gen_helper_dmt(t0, t0);
> > + gen_store_gpr(t0, rt);
> > break;
> > case OPC_EMT:
> > check_insn(env, ctx, ASE_MT);
> > gen_helper_emt(t0, t0);
> > + gen_store_gpr(t0, rt);
> > break;
> > case OPC_DVPE:
> > check_insn(env, ctx, ASE_MT);
> > gen_helper_dvpe(t0, t0);
> > + gen_store_gpr(t0, rt);
> > break;
> > case OPC_EVPE:
> > check_insn(env, ctx, ASE_MT);
> > gen_helper_evpe(t0, t0);
> > + gen_store_gpr(t0, rt);
> > break;
> > case OPC_DI:
> > check_insn(env, ctx, ISA_MIPS32R2);
> > - save_cpu_state(ctx, 1);
> save_cpu_state needed?
> > gen_helper_di(t0);
> > + gen_store_gpr(t0, rt);
> > /* Stop translation as we may have switched the execution mode */
> > ctx->bstate = BS_STOP;
> > break;
> > case OPC_EI:
> > check_insn(env, ctx, ISA_MIPS32R2);
> > - save_cpu_state(ctx, 1);
> save_cpu_state needed?
> > gen_helper_ei(t0);
> > + gen_store_gpr(t0, rt);
> > /* Stop translation as we may have switched the execution mode */
> > ctx->bstate = BS_STOP;
> > break;
> > @@ -7787,7 +7795,6 @@
> > generate_exception(ctx, EXCP_RI);
> > break;
> > }
> > - gen_store_gpr(t0, rt);
> > tcg_temp_free(t0);
> > }
> > #endif /* !CONFIG_USER_ONLY */
> > @@ -7839,7 +7846,6 @@
> > case OPC_SWC1:
> > case OPC_SDC1:
> > if (env->CP0_Config1 & (1 << CP0C1_FP)) {
> > - save_cpu_state(ctx, 1);
> > check_cp1_enabled(ctx);
> > gen_flt_ldst(ctx, op, rt, rs, imm);
> > } else {
> > @@ -7849,7 +7855,6 @@
> >
> > case OPC_CP1:
> > if (env->CP0_Config1 & (1 << CP0C1_FP)) {
> > - save_cpu_state(ctx, 1);
> > check_cp1_enabled(ctx);
> > op1 = MASK_CP1(ctx->opcode);
> > switch (op1) {
> > @@ -7908,7 +7913,6 @@
> >
> > case OPC_CP3:
> > if (env->CP0_Config1 & (1 << CP0C1_FP)) {
> > - save_cpu_state(ctx, 1);
> > check_cp1_enabled(ctx);
> > op1 = MASK_CP3(ctx->opcode);
> > switch (op1) {
> >
>
> This patch breaks Linux boot (fatal kernel error during boot,
> wrong kernel mode?). I'm sorry that I cannot give more
> details at the moment because I have trouble with
> my test hardware.
>
> Tested with QEMU trunk, mips little endian, malta machine.
>
> Re-adding the two removed calls of save_cpu_state (for
> OPC_DI, OPC_EI) lets the kernel boot again.
> Maybe there is a better fix.
>
Reverting those parts is actually the correct fix. I have remove the
calls to save_cpu_states() for helpers that can't trigger an exception,
but I forget to consider the case where those helpers are rising an
interrupt, calling in fine cpu_unlink_tb().
Strangely my test image was still working here, probably because I only
tried with a kernel without R2 support.
That should be fixed in the SVN now.
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 3+ messages in thread
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2009-04-08 21:47 [Qemu-devel] [7042] target-mips: optimize decode_opc() Aurelien Jarno
2009-04-12 20:14 ` Stefan Weil
2009-04-13 8:53 ` Aurelien Jarno
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