From: Aurelien Jarno <aurelien@aurel32.net>
To: Tristan Gingold <gingold@adacore.com>
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 05/19] Split cpu_mmu_index into cpu_mmu_index_data and cpu_mmu_index_code.
Date: Wed, 15 Apr 2009 16:30:42 +0200 [thread overview]
Message-ID: <20090415143042.GA13794@volta.aurel32.net> (raw)
In-Reply-To: <1238423794-25455-6-git-send-email-gingold@adacore.com>
On Mon, Mar 30, 2009 at 04:36:20PM +0200, Tristan Gingold wrote:
> This is required by alpha system emulation as PAL mode disable instruction
> mmu but not data mmu.
> This might also be required for other cpus that have a split I/D mmu enable.
>
> Signed-off-by: Tristan Gingold <gingold@adacore.com>
> ---
> exec-all.h | 2 +-
> softmmu_header.h | 4 ++--
> target-alpha/cpu.h | 13 +++++++++++--
> target-alpha/op_helper.c | 4 ++--
> target-arm/cpu.h | 3 ++-
> target-cris/cpu.h | 3 ++-
> target-cris/translate.c | 6 +++---
> target-i386/cpu.h | 3 ++-
> target-m68k/cpu.h | 3 ++-
> target-mips/cpu.h | 3 ++-
> target-ppc/cpu.h | 3 ++-
> target-sh4/cpu.h | 3 ++-
> target-sparc/cpu.h | 3 ++-
> target-sparc/translate.c | 2 +-
> 14 files changed, 36 insertions(+), 19 deletions(-)
>
> diff --git a/exec-all.h b/exec-all.h
> index 143aca1..a661cb1 100644
> --- a/exec-all.h
> +++ b/exec-all.h
> @@ -318,7 +318,7 @@ static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
> int mmu_idx, page_index, pd;
>
> page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
> - mmu_idx = cpu_mmu_index(env1);
> + mmu_idx = cpu_mmu_index_code(env1);
> if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
> (addr & TARGET_PAGE_MASK))) {
> ldub_code(addr);
> diff --git a/softmmu_header.h b/softmmu_header.h
> index a1b3808..f6f83da 100644
> --- a/softmmu_header.h
> +++ b/softmmu_header.h
> @@ -46,12 +46,12 @@
>
> #elif ACCESS_TYPE == (NB_MMU_MODES)
>
> -#define CPU_MMU_INDEX (cpu_mmu_index(env))
> +#define CPU_MMU_INDEX (cpu_mmu_index_data(env))
> #define MMUSUFFIX _mmu
>
> #elif ACCESS_TYPE == (NB_MMU_MODES + 1)
>
> -#define CPU_MMU_INDEX (cpu_mmu_index(env))
> +#define CPU_MMU_INDEX (cpu_mmu_index_code(env))
> #define MMUSUFFIX _cmmu
>
> #else
> diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
> index 582827e..3798157 100644
> --- a/target-alpha/cpu.h
> +++ b/target-alpha/cpu.h
> @@ -331,16 +331,25 @@ struct CPUAlphaState {
> #define cpu_exec cpu_alpha_exec
> #define cpu_gen_code cpu_alpha_gen_code
> #define cpu_signal_handler cpu_alpha_signal_handler
> +#define cpu_list alpha_cpu_list
>
> /* MMU modes definitions */
> #define MMU_MODE0_SUFFIX _kernel
> #define MMU_MODE1_SUFFIX _executive
> #define MMU_MODE2_SUFFIX _supervisor
> #define MMU_MODE3_SUFFIX _user
> +#define MMU_MODE4_SUFFIX _pal
> +#define MMU_KERNEL_IDX 0
> #define MMU_USER_IDX 3
> -static inline int cpu_mmu_index (CPUState *env)
> +#define MMU_PAL_IDX 4
> +static inline int cpu_mmu_index_data (CPUState *env)
> {
> - return (env->ps >> 3) & 3;
> + return env->mmu_data_index;
> +}
> +
> +static inline int cpu_mmu_index_code (CPUState *env)
> +{
> + return env->mmu_code_index;
> }
>From where env->mmu_data_index and env->mmu_code_index come from? After
applying this patch, I get:
CC main.o
In file included from /home/aurel32/git/qemu/linux-user/qemu.h:8,
from /home/aurel32/git/qemu/linux-user/main.c:30:
/home/aurel32/git/qemu/target-alpha/cpu.h: In function 'cpu_mmu_index_data':
/home/aurel32/git/qemu/target-alpha/cpu.h:347: error: 'struct CPUAlphaState' has no member named 'mmu_data_index'
/home/aurel32/git/qemu/target-alpha/cpu.h: In function 'cpu_mmu_index_code':
/home/aurel32/git/qemu/target-alpha/cpu.h:352: error: 'struct CPUAlphaState' has no member named 'mmu_code_index'
/home/aurel32/git/qemu/linux-user/main.c: In function 'main':
/home/aurel32/git/qemu/linux-user/main.c:2359: warning: implicit declaration of function 'alpha_cpu_list'
make: *** [main.o] Error 1
> #if defined(CONFIG_USER_ONLY)
> diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c
> index 7ad1b3d..433a0da 100644
> --- a/target-alpha/op_helper.c
> +++ b/target-alpha/op_helper.c
> @@ -1049,7 +1049,7 @@ uint64_t helper_ld_virt_to_phys (uint64_t virtaddr)
> int index, mmu_idx;
> void *retaddr;
>
> - mmu_idx = cpu_mmu_index(env);
> + mmu_idx = cpu_mmu_index_data(env);
> index = (virtaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
> redo:
> tlb_addr = env->tlb_table[mmu_idx][index].addr_read;
> @@ -1071,7 +1071,7 @@ uint64_t helper_st_virt_to_phys (uint64_t virtaddr)
> int index, mmu_idx;
> void *retaddr;
>
> - mmu_idx = cpu_mmu_index(env);
> + mmu_idx = cpu_mmu_index_data(env);
> index = (virtaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
> redo:
> tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index f98655f..c0cfb8d 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -412,7 +412,8 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
> #define MMU_MODE0_SUFFIX _kernel
> #define MMU_MODE1_SUFFIX _user
> #define MMU_USER_IDX 1
> -static inline int cpu_mmu_index (CPUState *env)
> +#define cpu_mmu_index_data cpu_mmu_index_code
> +static inline int cpu_mmu_index_code (CPUState *env)
> {
> return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
> }
> diff --git a/target-cris/cpu.h b/target-cris/cpu.h
> index e98a48d..807a55a 100644
> --- a/target-cris/cpu.h
> +++ b/target-cris/cpu.h
> @@ -212,7 +212,8 @@ enum {
> #define MMU_MODE0_SUFFIX _kernel
> #define MMU_MODE1_SUFFIX _user
> #define MMU_USER_IDX 1
> -static inline int cpu_mmu_index (CPUState *env)
> +#define cpu_mmu_index_data cpu_mmu_index_code
> +static inline int cpu_mmu_index_code (CPUState *env)
> {
> return !!(env->pregs[PR_CCS] & U_FLAG);
> }
> diff --git a/target-cris/translate.c b/target-cris/translate.c
> index d5fcb9e..20699e9 100644
> --- a/target-cris/translate.c
> +++ b/target-cris/translate.c
> @@ -1104,7 +1104,7 @@ static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
>
> static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
> {
> - int mem_index = cpu_mmu_index(dc->env);
> + int mem_index = cpu_mmu_index_data(dc->env);
>
> /* If we get a fault on a delayslot we must keep the jmp state in
> the cpu-state to be able to re-execute the jmp. */
> @@ -1117,7 +1117,7 @@ static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
> static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
> unsigned int size, int sign)
> {
> - int mem_index = cpu_mmu_index(dc->env);
> + int mem_index = cpu_mmu_index_data(dc->env);
>
> /* If we get a fault on a delayslot we must keep the jmp state in
> the cpu-state to be able to re-execute the jmp. */
> @@ -1147,7 +1147,7 @@ static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
> static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
> unsigned int size)
> {
> - int mem_index = cpu_mmu_index(dc->env);
> + int mem_index = cpu_mmu_index_data(dc->env);
>
> /* If we get a fault on a delayslot we must keep the jmp state in
> the cpu-state to be able to re-execute the jmp. */
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index 90bceab..f3ccb53 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -842,7 +842,8 @@ static inline int cpu_get_time_fast(void)
> #define MMU_MODE0_SUFFIX _kernel
> #define MMU_MODE1_SUFFIX _user
> #define MMU_USER_IDX 1
> -static inline int cpu_mmu_index (CPUState *env)
> +#define cpu_mmu_index_data cpu_mmu_index_code
> +static inline int cpu_mmu_index_code (CPUState *env)
> {
> return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0;
> }
> diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
> index e2529eb..94af716 100644
> --- a/target-m68k/cpu.h
> +++ b/target-m68k/cpu.h
> @@ -218,7 +218,8 @@ void register_m68k_insns (CPUM68KState *env);
> #define MMU_MODE0_SUFFIX _kernel
> #define MMU_MODE1_SUFFIX _user
> #define MMU_USER_IDX 1
> -static inline int cpu_mmu_index (CPUState *env)
> +#define cpu_mmu_index_data cpu_mmu_index_code
> +static inline int cpu_mmu_index_code (CPUState *env)
> {
> return (env->sr & SR_S) == 0 ? 1 : 0;
> }
> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> index b415dc4..a793166 100644
> --- a/target-mips/cpu.h
> +++ b/target-mips/cpu.h
> @@ -489,7 +489,8 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
> #define MMU_MODE1_SUFFIX _super
> #define MMU_MODE2_SUFFIX _user
> #define MMU_USER_IDX 2
> -static inline int cpu_mmu_index (CPUState *env)
> +#define cpu_mmu_index_data cpu_mmu_index_code
> +static inline int cpu_mmu_index_code (CPUState *env)
> {
> return env->hflags & MIPS_HFLAG_KSU;
> }
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 87b3460..4d75ced 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -809,7 +809,8 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
> #define MMU_MODE1_SUFFIX _kernel
> #define MMU_MODE2_SUFFIX _hypv
> #define MMU_USER_IDX 0
> -static inline int cpu_mmu_index (CPUState *env)
> +#define cpu_mmu_index_data cpu_mmu_index_code
> +static inline int cpu_mmu_index_code (CPUState *env)
> {
> return env->mmu_idx;
> }
> diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
> index aea7108..eaae3cf 100644
> --- a/target-sh4/cpu.h
> +++ b/target-sh4/cpu.h
> @@ -181,7 +181,8 @@ void cpu_load_tlb(CPUSH4State * env);
> #define MMU_MODE0_SUFFIX _kernel
> #define MMU_MODE1_SUFFIX _user
> #define MMU_USER_IDX 1
> -static inline int cpu_mmu_index (CPUState *env)
> +#define cpu_mmu_index_data cpu_mmu_index_code
> +static inline int cpu_mmu_index_code (CPUState *env)
> {
> return (env->sr & SR_MD) == 0 ? 1 : 0;
> }
> diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
> index 8b84789..33cf4c3 100644
> --- a/target-sparc/cpu.h
> +++ b/target-sparc/cpu.h
> @@ -456,7 +456,8 @@ int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
> #define MMU_KERNEL_IDX 1
> #define MMU_HYPV_IDX 2
>
> -static inline int cpu_mmu_index(CPUState *env1)
> +#define cpu_mmu_index_data cpu_mmu_index_code
> +static inline int cpu_mmu_index_code(CPUState *env1)
> {
> #if defined(CONFIG_USER_ONLY)
> return MMU_USER_IDX;
> diff --git a/target-sparc/translate.c b/target-sparc/translate.c
> index d059408..017c375 100644
> --- a/target-sparc/translate.c
> +++ b/target-sparc/translate.c
> @@ -4769,7 +4769,7 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb,
> dc->pc = pc_start;
> last_pc = dc->pc;
> dc->npc = (target_ulong) tb->cs_base;
> - dc->mem_idx = cpu_mmu_index(env);
> + dc->mem_idx = cpu_mmu_index_code(env);
> dc->def = env->def;
> if ((dc->def->features & CPU_FEATURE_FLOAT))
> dc->fpu_enabled = cpu_fpu_enabled(env);
> --
> 1.6.2
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
next prev parent reply other threads:[~2009-04-15 14:30 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-03-30 14:36 [Qemu-devel] [PATCH 0/20]: add alpha es40 system emulation (v4) Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 01/19] Add support for multi-level phys map Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 02/19] Increase Alpha physical address size to 44 bits Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 03/19] Alpha: set target page size to 13 bits Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 04/19] Allow 5 mmu indexes Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 05/19] Split cpu_mmu_index into cpu_mmu_index_data and cpu_mmu_index_code Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 06/19] Bug fix alpha: stop translation if too long Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 07/19] Alpha bug: fix palcode mask for user pal calls Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 08/19] Alpha: document more registers used by 21264 Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 09/19] Add square wave output support Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 10/19] Add ali1543 super IO pci device Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 11/19] Add 21272 chipset (memory and pci controller for alpha) Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 12/19] Add target-alpha/machine.c and hw/es40.c for es40 machine emulation Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 13/19] Move softmmu_helper.h from exec.h to op_helper.c on alpha Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 14/19] alpha ld helpers now directly return the value Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 15/19] Add alpha_cpu_list Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 16/19] Alpha: lower parent irq when irq is lowered Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 17/19] Move linux-user pal emulation to linux-user/ Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 18/19] Correctly decode hw_ld/hw_st opcodes for all alpha implementations Tristan Gingold
2009-03-30 14:36 ` [Qemu-devel] [PATCH 19/19] Add full emulation for 21264 Tristan Gingold
2009-04-07 21:52 ` [Qemu-devel] [PATCH 18/19] Correctly decode hw_ld/hw_st opcodes for all alpha implementations Aurelien Jarno
2009-04-08 12:26 ` Tristan Gingold
2009-04-15 14:42 ` [Qemu-devel] [PATCH 16/19] Alpha: lower parent irq when irq is lowered Aurelien Jarno
2009-04-07 22:29 ` [Qemu-devel] [PATCH 09/19] Add square wave output support Aurelien Jarno
2009-04-07 22:32 ` [Qemu-devel] [PATCH 08/19] Alpha: document more registers used by 21264 Aurelien Jarno
2009-04-07 22:31 ` [Qemu-devel] [PATCH 07/19] Alpha bug: fix palcode mask for user pal calls Aurelien Jarno
2009-04-07 21:44 ` [Qemu-devel] [PATCH 06/19] Bug fix alpha: stop translation if too long Aurelien Jarno
2009-04-15 14:30 ` Aurelien Jarno [this message]
2009-04-21 12:10 ` [Qemu-devel] [PATCH 05/19] Split cpu_mmu_index into cpu_mmu_index_data and cpu_mmu_index_code Tristan Gingold
2009-04-07 21:48 ` [Qemu-devel] [PATCH 04/19] Allow 5 mmu indexes Aurelien Jarno
2009-04-07 21:47 ` [Qemu-devel] [PATCH 03/19] Alpha: set target page size to 13 bits Aurelien Jarno
2009-04-15 16:23 ` [Qemu-devel] [PATCH 01/19] Add support for multi-level phys map Aurelien Jarno
2009-04-21 12:11 ` Tristan Gingold
2009-03-30 15:46 ` [Qemu-devel] [PATCH 0/20]: add alpha es40 system emulation (v4) Brian Wheeler
2009-03-30 16:04 ` Tristan Gingold
2009-03-30 16:43 ` Brian Wheeler
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