[Qemu-devel] Re: [PATCH 05/15] Coalesce userspace/kernel irqchip interrupt injection logic.

[Gleb Natapov <gleb@redhat.com>]

On Sun, Apr 19, 2009 at 04:05:21PM +0200, Jan Kiszka wrote:
> > And this is not the only problem I saw, but the one that caused my guest
> > to hang.
> 
> OK, good to know. I added Alex (though he's said to be on vacation ATM)
> and qemu to CC. Maybe you can quickly list the other issues you've
> stumbled over, for the records and for motivating contributors...
> 
Another one that I remember (because this was my first suspect) is
interrupt shadow handling. HF_INHIBIT_IRQ_MASK is cleared on exit when
shadow bit is set in int_state and is not set on entry if hypervisor
set shadow bit by itself. I am not sure how real HW actually handles this,
but patch below demonstrates how I think it does it :) And of cause
comments like /* FIXME: this should respect TPR */ don't look promising.


diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c
index be09263..691a7f0 100644
--- a/target-i386/op_helper.c
+++ b/target-i386/op_helper.c
@@ -4971,6 +4997,15 @@ void helper_vmrun(int aflag, int next_eip_addend)
     env->dr[6] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr6));
     cpu_x86_set_cpl(env, ldub_phys(env->vm_vmcb + offsetof(struct vmcb, save.cpl)));
 
+    {
+	uint32_t aaa;
+        aaa = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_state));
+	if (aaa & SVM_INTERRUPT_SHADOW_MASK)
+		helper_set_inhibit_irq();
+	else
+		helper_reset_inhibit_irq();
+    }
+
     /* FIXME: guest state consistency checks */
 
     switch(ldub_phys(env->vm_vmcb + offsetof(struct vmcb, control.tlb_ctl))) {
@@ -5243,7 +5280,6 @@ void helper_vmexit(uint32_t exit_code, uint64_t exit_info_1)
 
     if(env->hflags & HF_INHIBIT_IRQ_MASK) {
         stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_state), SVM_INTERRUPT_SHADOW_MASK);
-        env->hflags &= ~HF_INHIBIT_IRQ_MASK;
     } else {
         stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_state), 0);
     }
--
			Gleb.