From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LvY0I-0002KE-2O for qemu-devel@nongnu.org; Sun, 19 Apr 2009 10:28:18 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LvY0C-0002Jz-Ix for qemu-devel@nongnu.org; Sun, 19 Apr 2009 10:28:16 -0400 Received: from [199.232.76.173] (port=36135 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LvY0C-0002Ju-Cn for qemu-devel@nongnu.org; Sun, 19 Apr 2009 10:28:12 -0400 Received: from mx2.redhat.com ([66.187.237.31]:36836) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1LvY0B-0002IC-VD for qemu-devel@nongnu.org; Sun, 19 Apr 2009 10:28:12 -0400 Date: Sun, 19 Apr 2009 17:28:04 +0300 From: Gleb Natapov Message-ID: <20090419142804.GQ10126@redhat.com> References: <1239616545-25199-1-git-send-email-gleb@redhat.com> <1239616545-25199-6-git-send-email-gleb@redhat.com> <49E99A7F.7000902@web.de> <20090418162820.GI27675@redhat.com> <20090419135745.GO10126@redhat.com> <49EB2FA1.2090305@web.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <49EB2FA1.2090305@web.de> Subject: [Qemu-devel] Re: [PATCH 05/15] Coalesce userspace/kernel irqchip interrupt injection logic. Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Jan Kiszka Cc: kvm@vger.kernel.org, Dmitry Eremin-Solenikov , Joerg Roedel , qemu-devel , Alexander Graf , Avi Kivity On Sun, Apr 19, 2009 at 04:05:21PM +0200, Jan Kiszka wrote: > > And this is not the only problem I saw, but the one that caused my guest > > to hang. > > OK, good to know. I added Alex (though he's said to be on vacation ATM) > and qemu to CC. Maybe you can quickly list the other issues you've > stumbled over, for the records and for motivating contributors... > Another one that I remember (because this was my first suspect) is interrupt shadow handling. HF_INHIBIT_IRQ_MASK is cleared on exit when shadow bit is set in int_state and is not set on entry if hypervisor set shadow bit by itself. I am not sure how real HW actually handles this, but patch below demonstrates how I think it does it :) And of cause comments like /* FIXME: this should respect TPR */ don't look promising. diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c index be09263..691a7f0 100644 --- a/target-i386/op_helper.c +++ b/target-i386/op_helper.c @@ -4971,6 +4997,15 @@ void helper_vmrun(int aflag, int next_eip_addend) env->dr[6] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.dr6)); cpu_x86_set_cpl(env, ldub_phys(env->vm_vmcb + offsetof(struct vmcb, save.cpl))); + { + uint32_t aaa; + aaa = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_state)); + if (aaa & SVM_INTERRUPT_SHADOW_MASK) + helper_set_inhibit_irq(); + else + helper_reset_inhibit_irq(); + } + /* FIXME: guest state consistency checks */ switch(ldub_phys(env->vm_vmcb + offsetof(struct vmcb, control.tlb_ctl))) { @@ -5243,7 +5280,6 @@ void helper_vmexit(uint32_t exit_code, uint64_t exit_info_1) if(env->hflags & HF_INHIBIT_IRQ_MASK) { stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_state), SVM_INTERRUPT_SHADOW_MASK); - env->hflags &= ~HF_INHIBIT_IRQ_MASK; } else { stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_state), 0); } -- Gleb.