From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Lx31s-00014m-3y for qemu-devel@nongnu.org; Thu, 23 Apr 2009 13:48:08 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Lx31r-00014Q-Ff for qemu-devel@nongnu.org; Thu, 23 Apr 2009 13:48:07 -0400 Received: from [199.232.76.173] (port=42661 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Lx31r-00014H-7M for qemu-devel@nongnu.org; Thu, 23 Apr 2009 13:48:07 -0400 Received: from flounder.pepperfish.net ([87.237.62.181]:42135) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Lx31q-0002PE-LP for qemu-devel@nongnu.org; Thu, 23 Apr 2009 13:48:06 -0400 Received: from [10.112.102.2] (helo=jennifer.kylikki.org) by flounder.pepperfish.net with esmtps (Exim 4.69 #1 (Debian)) id 1Lx31o-0001k1-Kq for ; Thu, 23 Apr 2009 18:48:04 +0100 Received: from derik.kyllikki.org ([192.168.7.20] helo=derik) by jennifer.kylikki.org with esmtp (Exim 4.63) (envelope-from ) id 1Lx31p-0005m6-0Z for qemu-devel@nongnu.org; Thu, 23 Apr 2009 18:48:05 +0100 Received: from vince by derik with local (Exim 4.69) (envelope-from ) id 1Lx31o-0003fz-V4 for qemu-devel@nongnu.org; Thu, 23 Apr 2009 18:48:04 +0100 Date: Thu, 23 Apr 2009 18:48:04 +0100 From: Vincent Sanders Subject: [Qemu-devel] [PATCH 2/16] Add s3c SOC header Message-ID: <20090423174804.GE4629@derik> References: <20090423171503.GC4629@derik> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090423171503.GC4629@derik> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org S3C SOC integrated peripheral devices structure Signed-off-by: Vincent Sanders --- s3c24xx.h | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff -urN qemusvnclean/hw/s3c24xx.h qemusvnpatches/hw/s3c24xx.h --- qemusvnclean/hw/s3c24xx.h 1970-01-01 01:00:00.000000000 +0100 +++ qemusvnpatches/hw/s3c24xx.h 2009-04-23 15:53:57.000000000 +0100 @@ -0,0 +1,73 @@ +/* hw/s3c24xx.h + * + * Samsung s3c24xx cpu state and functions. + * + * Copyright 2006, 2007, 2008 Daniel Silverstone and Vincent Sanders + * + * This file is under the terms of the GNU General Public + * License Version 2. + */ + +#ifndef S3C24XX_H +#define S3C24XX_H 1 + +/* This structure type encapsulates the state of a S3C24XX SoC. */ +typedef struct S3CState_s { + CPUState *cpu_env; + qemu_irq *irqs; + qemu_irq *eirqs; + + /* Memory controller */ + uint32_t memc_reg[13]; + + /* Interrupt controller */ + uint32_t irq_main_level, irq_subsrc_level; + uint32_t irq_reg[8]; + + /* Clock controller */ + uint32_t clkcon_reg[6]; + + uint32_t tclk0; /* first timer clock source frequency */ + uint32_t tclk1; /* second timer clock source frequency */ + + /* GPIO block */ + uint32_t gpio_reg[47]; + + /* Realtime clock */ + uint8_t rtc_reg[19]; + + /* i2c */ + struct s3c24xx_i2c_state_s *iic; + + /* Timers, (Specifically timer4) */ + uint32_t timers_reg[17]; + QEMUTimer *timer4; + uint32_t timer4_reload_value; + int64_t timer4_last_ticked; + + /* LCD controller */ + struct s3c24xx_lcd_state_s *lcd; + + /* NAND controller, and chip attached */ + uint32_t nand_reg[5]; + struct nand_flash_s *nand_chip; +} S3CState; + +/* Internal functions for s3c24xx implementation */ +void s3c24xx_memc_init(S3CState *soc, target_phys_addr_t base_addr); +qemu_irq *s3c24xx_irq_init(S3CState *soc, target_phys_addr_t base_addr); +void s3c24xx_clkcon_init(S3CState *soc, target_phys_addr_t base_addr); +void s3c24xx_timers_init(S3CState *soc, target_phys_addr_t base_addr); +void s3c24xx_serial_init(S3CState *soc, int port, target_phys_addr_t base_addr); +void s3c24xx_rtc_init(S3CState *soc, target_phys_addr_t base_addr); +void s3c24xx_gpio_init(S3CState *soc, target_phys_addr_t base_addr,uint32_t cpu_id ); +void s3c24xx_iic_init(S3CState *soc, target_phys_addr_t base_addr); +struct s3c24xx_lcd_state_s *s3c24xx_lcd_init(target_phys_addr_t base, qemu_irq irq); +void s3c24xx_nand_init(S3CState *soc, target_phys_addr_t base_addr); + +/* attach a NAND device to the s3c24xx controller */ +void s3c24xx_nand_attach(S3CState *soc, struct nand_flash_s *nand_chip); + +i2c_bus *s3c24xx_i2c_bus(struct s3c24xx_i2c_state_s *s); + +#endif /* S3C24XX_H */ -- Regards Vincent http://www.kyllikki.org/