From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Lx344-0001mB-5k for qemu-devel@nongnu.org; Thu, 23 Apr 2009 13:50:24 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Lx343-0001ln-Ir for qemu-devel@nongnu.org; Thu, 23 Apr 2009 13:50:23 -0400 Received: from [199.232.76.173] (port=57402 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Lx343-0001lg-CQ for qemu-devel@nongnu.org; Thu, 23 Apr 2009 13:50:23 -0400 Received: from flounder.pepperfish.net ([87.237.62.181]:48805) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Lx342-0002jO-Dm for qemu-devel@nongnu.org; Thu, 23 Apr 2009 13:50:23 -0400 Received: from [10.112.102.2] (helo=jennifer.kylikki.org) by flounder.pepperfish.net with esmtps (Exim 4.69 #1 (Debian)) id 1Lx340-0002M5-At for ; Thu, 23 Apr 2009 18:50:20 +0100 Received: from derik.kyllikki.org ([192.168.7.20] helo=derik) by jennifer.kylikki.org with esmtp (Exim 4.63) (envelope-from ) id 1Lx340-0005uA-N6 for qemu-devel@nongnu.org; Thu, 23 Apr 2009 18:50:20 +0100 Received: from vince by derik with local (Exim 4.69) (envelope-from ) id 1Lx340-0003mN-LO for qemu-devel@nongnu.org; Thu, 23 Apr 2009 18:50:20 +0100 Date: Thu, 23 Apr 2009 18:50:20 +0100 From: Vincent Sanders Subject: [Qemu-devel] [PATCH 3/16] S3C SDRAM memory controller Peripheral Message-ID: <20090423175020.GF4629@derik> References: <20090423171503.GC4629@derik> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090423171503.GC4629@derik> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Peripheral driver for S3C SOC SDRAM controller. Signed-off-by: Vincent Sanders --- s3c24xx_memc.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff -urN qemusvnclean/hw/s3c24xx_memc.c qemusvnpatches/hw/s3c24xx_memc.c --- qemusvnclean/hw/s3c24xx_memc.c 1970-01-01 01:00:00.000000000 +0100 +++ qemusvnpatches/hw/s3c24xx_memc.c 2009-04-23 15:57:46.000000000 +0100 @@ -0,0 +1,70 @@ +/* hw/s3c24xx_memc.c + * + * Samsung S3C24XX memory controller emulation. + * + * The SDRAM controller on several S3C SOC is generic, the emulation needs to + * be little more than backing the registers. + * + * Copyright 2006, 2007 Daniel Silverstone and Vincent Sanders + * + * This file is under the terms of the GNU General Public + * License Version 2 + */ + +#include "hw.h" + +#include "s3c24xx.h" + +static void +s3c24xx_memc_write_f(void *opaque, target_phys_addr_t addr_, uint32_t value) +{ + S3CState *soc = (S3CState *)opaque; + int addr = (addr_ & 0x3f) >> 2; + + if (addr < 0 || addr > 12) + addr = 12; + + soc->memc_reg[addr] = value; +} + +static uint32_t +s3c24xx_memc_read_f(void *opaque, target_phys_addr_t addr_) +{ + S3CState *soc = (S3CState *)opaque; + int addr = (addr_ & 0x3f) >> 2; + + if (addr < 0 || addr > 12) + addr = 12; + + return soc->memc_reg[addr]; +} + +static CPUReadMemoryFunc *s3c24xx_memc_read[] = { + &s3c24xx_memc_read_f, + &s3c24xx_memc_read_f, + &s3c24xx_memc_read_f, +}; + +static CPUWriteMemoryFunc *s3c24xx_memc_write[] = { + &s3c24xx_memc_write_f, + &s3c24xx_memc_write_f, + &s3c24xx_memc_write_f, +}; + + +void +s3c24xx_memc_init(S3CState *soc, target_phys_addr_t base_addr) +{ + /* Memory controller is simple SDRAM control. As SDRAM is emulated and + * requires no setup the emulation needs to be nothing more than memory + * backing the registers. + * + * There are 13 registers, each 4 bytes. + */ + int tag; + tag = cpu_register_io_memory(0, s3c24xx_memc_read, s3c24xx_memc_write, soc); + cpu_register_physical_memory(base_addr, 13 * 4, tag); + + for (tag = 0; tag < 13; tag++) + soc->memc_reg[tag] = 0; +} -- Regards Vincent http://www.kyllikki.org/