From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Lx3Br-0004GU-4c for qemu-devel@nongnu.org; Thu, 23 Apr 2009 13:58:27 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Lx3Bq-0004Fy-Bx for qemu-devel@nongnu.org; Thu, 23 Apr 2009 13:58:26 -0400 Received: from [199.232.76.173] (port=37628 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Lx3Bq-0004Fm-1c for qemu-devel@nongnu.org; Thu, 23 Apr 2009 13:58:26 -0400 Received: from flounder.pepperfish.net ([87.237.62.181]:41700) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Lx3Bp-0003zw-Cf for qemu-devel@nongnu.org; Thu, 23 Apr 2009 13:58:25 -0400 Received: from [10.112.102.2] (helo=jennifer.kylikki.org) by flounder.pepperfish.net with esmtps (Exim 4.69 #1 (Debian)) id 1Lx3Bn-0003QQ-Bl for ; Thu, 23 Apr 2009 18:58:23 +0100 Received: from derik.kyllikki.org ([192.168.7.20] helo=derik) by jennifer.kylikki.org with esmtp (Exim 4.63) (envelope-from ) id 1Lx3Bn-00063A-QK for qemu-devel@nongnu.org; Thu, 23 Apr 2009 18:58:23 +0100 Received: from vince by derik with local (Exim 4.69) (envelope-from ) id 1Lx3Bn-0003uE-OQ for qemu-devel@nongnu.org; Thu, 23 Apr 2009 18:58:23 +0100 Date: Thu, 23 Apr 2009 18:58:23 +0100 From: Vincent Sanders Subject: [Qemu-devel] [PATCH 05/16] S3C Clock controller peripheral Message-ID: <20090423175823.GH4629@derik> References: <20090423171503.GC4629@derik> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090423171503.GC4629@derik> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org S3C Clock control support. Signed-off-by: Vincent Sanders --- s3c24xx_clkcon.c | 100 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff -urN qemusvnclean/hw/s3c24xx_clkcon.c qemusvnpatches/hw/s3c24xx_clkcon.c --- qemusvnclean/hw/s3c24xx_clkcon.c 1970-01-01 01:00:00.000000000 +0100 +++ qemusvnpatches/hw/s3c24xx_clkcon.c 2009-04-23 16:00:56.000000000 +0100 @@ -0,0 +1,100 @@ +/* hw/s3c24xx_clkcon.c + * + * Samsung S3C24XX Clock control emulation + * + * Copyright 2006, 2007, 2008 Daniel Silverstone and Vincent Sanders + * + * This file is under the terms of the GNU General Public + * License Version 2 + */ + +#include "hw.h" + +#include "s3c24xx.h" + +/* Lock time RW */ +#define S3C_REG_LOCKTIME 0 + +/* MPLL Control RW */ +#define S3C_REG_MPLLCON 1 + +/* UPLL Control RW */ +#define S3C_REG_UPLLCON 2 + +/* Clock Generator Control RW */ +#define S3C_REG_CLKCON 3 + +/* CLKCON IDLE */ +#define S3C_REG_CLKCON_IDLE (1<<2) + +/* Slow Clock Control RW */ +#define S3C_REG_CLKSLOW 4 + +/* Clock divider control RW */ +#define S3C_REG_CLKDIVN 5 + +static void +s3c24xx_clkcon_write_f(void *opaque, target_phys_addr_t addr_, uint32_t value) +{ + S3CState *soc = (S3CState *)opaque; + int addr = (addr_ & 0x1F) >> 2; + int idle_rising_edge = 0; + + if (addr < 0 || addr > 5) + addr = 5; + + if (addr == S3C_REG_CLKCON) { + if( !(soc->clkcon_reg[addr] & S3C_REG_CLKCON_IDLE) && + (value & S3C_REG_CLKCON_IDLE) ) idle_rising_edge = 1; + } + soc->clkcon_reg[addr] = value; + if (idle_rising_edge) { + cpu_interrupt(soc->cpu_env, CPU_INTERRUPT_HALT); + } +} + +static uint32_t +s3c24xx_clkcon_read_f(void *opaque, target_phys_addr_t addr_) +{ + S3CState *soc = (S3CState *)opaque; + int addr = (addr_ & 0x1F) >> 2; + + if (addr < 0 || addr > 5) + addr = 5; + + return soc->clkcon_reg[addr]; +} + +static CPUReadMemoryFunc *s3c24xx_clkcon_read[] = { + &s3c24xx_clkcon_read_f, + &s3c24xx_clkcon_read_f, + &s3c24xx_clkcon_read_f, +}; + +static CPUWriteMemoryFunc *s3c24xx_clkcon_write[] = { + &s3c24xx_clkcon_write_f, + &s3c24xx_clkcon_write_f, + &s3c24xx_clkcon_write_f, +}; + + +void +s3c24xx_clkcon_init(S3CState *soc, target_phys_addr_t base_addr) +{ + int tag; + + tag = cpu_register_io_memory(0, s3c24xx_clkcon_read, s3c24xx_clkcon_write, soc); + cpu_register_physical_memory(base_addr, 6 * 4, tag); + + /* initialise register values to power on defaults */ + soc->clkcon_reg[S3C_REG_LOCKTIME] = 0x00FFFFFF; + soc->clkcon_reg[S3C_REG_MPLLCON] = 0x0005C080; + soc->clkcon_reg[S3C_REG_UPLLCON] = 0x00028080; + soc->clkcon_reg[S3C_REG_CLKCON] = 0x0007FFF0; + soc->clkcon_reg[S3C_REG_CLKSLOW] = 0x00000004; + soc->clkcon_reg[S3C_REG_CLKDIVN] = 0x00000000; + + /* Currently it is assumed the t1 clock will be fed by a 12MHz source */ + soc->tclk1 = 12000000; + +} -- Regards Vincent http://www.kyllikki.org/