From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Lx3RC-0002nI-Jv for qemu-devel@nongnu.org; Thu, 23 Apr 2009 14:14:18 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Lx3RB-0002mO-Es for qemu-devel@nongnu.org; Thu, 23 Apr 2009 14:14:17 -0400 Received: from [199.232.76.173] (port=60791 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Lx3RB-0002mB-4l for qemu-devel@nongnu.org; Thu, 23 Apr 2009 14:14:17 -0400 Received: from flounder.pepperfish.net ([87.237.62.181]:50303) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Lx3RA-0005xD-Hi for qemu-devel@nongnu.org; Thu, 23 Apr 2009 14:14:16 -0400 Received: from [10.112.102.2] (helo=jennifer.kylikki.org) by flounder.pepperfish.net with esmtps (Exim 4.69 #1 (Debian)) id 1Lx3R8-0005wI-2p for ; Thu, 23 Apr 2009 19:14:14 +0100 Received: from derik.kyllikki.org ([192.168.7.20] helo=derik) by jennifer.kylikki.org with esmtp (Exim 4.63) (envelope-from ) id 1Lx3R8-0006W1-Hl for qemu-devel@nongnu.org; Thu, 23 Apr 2009 19:14:14 +0100 Received: from vince by derik with local (Exim 4.69) (envelope-from ) id 1Lx3R8-0004Fi-Fr for qemu-devel@nongnu.org; Thu, 23 Apr 2009 19:14:14 +0100 Date: Thu, 23 Apr 2009 19:14:14 +0100 From: Vincent Sanders Subject: [Qemu-devel] [PATCH 14/16] S3C2440 SOC impementation Message-ID: <20090423181414.GQ4629@derik> References: <20090423171503.GC4629@derik> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090423171503.GC4629@derik> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org S3C2440 Implementation using generic S3C periperals. Signed-off-by: Vincent Sanders --- s3c2440x.c | 117 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ s3c2440x.h | 30 +++++++++++++++ 2 files changed, 147 insertions(+) diff -urN qemusvnclean/hw/s3c2440x.c qemusvnpatches/hw/s3c2440x.c --- qemusvnclean/hw/s3c2440x.c 1970-01-01 01:00:00.000000000 +0100 +++ qemusvnpatches/hw/s3c2440x.c 2009-04-23 17:25:05.000000000 +0100 @@ -0,0 +1,117 @@ +/* hw/s3c2440x.c + * + * Samsung S3C2440X emulation + * + * Copyright 2006, 2007 Daniel Silverstone and Vincent Sanders + * + * This file is under the terms of the GNU General Public + * License Version 2 + */ + +#include "hw.h" + +#include "s3c2440x.h" + +/* We use the PXA style OHCI USB mapping */ +#include "pxa.h" + +/* S3C2440 SoC IDs */ +#define CPU_S3C2440X_IDENT_S3C2440A 0x32440001 + +/* Integrated SOC peripherals */ + +/* SRAM */ +#define CPU_S3C2440X_SRAM_BASE (0x40000000) + +/* Memory control */ +#define CPU_S3C2440X_MEMC_BASE (0x48000000) + +/* USB controller */ +#define CPU_S3C2440X_OHCI (0x49000000) + +/* Interrupt controller */ +#define CPU_S3C2440X_IRQ_BASE (0x4A000000) + +/* Clock control */ +#define CPU_S3C2440X_CLKCON_BASE (0x4C000000) + +/* LCD */ +#define CPU_S3C2440X_LCD_BASE (0x4D000000) + +/* NAND */ +#define CPU_S3C2440X_NAND_BASE (0x4E000000) + +/* serial port base */ +#define CPU_S3C2440X_SERIAL_BASE (0x50000000) + +/* Timers */ +#define CPU_S3C2440X_TIMERS_BASE (0x51000000) + +/* Watchdog */ +#define CPU_S3C2440X_WDOG_BASE (0x53000000) + +/* IIC */ +#define CPU_S3C2440X_IIC_BASE (0x54000000) + +/* GPIO */ +#define CPU_S3C2440X_GPIO_BASE (0x56000000) + +/* Real time clock */ +#define CPU_S3C2440X_RTC_BASE (0x57000000) + +/* Initialise a Samsung S3C2440X SOC ARM core and internal peripherals. */ +S3CState * +s3c2440x_init(int sdram_size) +{ + S3CState *s = (S3CState *)qemu_mallocz(sizeof(S3CState)); + + /* Prepare the ARM 920T core */ + s->cpu_env = cpu_init("arm920t"); + + /* S3C2440X SDRAM memory is always at the same physical location */ + cpu_register_physical_memory(CPU_S3C2440X_RAM, + ram_size, + qemu_ram_alloc(sdram_size) | IO_MEM_RAM); + + /* Memory controller */ + s3c24xx_memc_init(s, CPU_S3C2440X_MEMC_BASE); + + /* S3C2440X SRAM */ + cpu_register_physical_memory(CPU_S3C2440X_SRAM_BASE, + 4096, + qemu_ram_alloc(4096) | IO_MEM_RAM); + + /* Add the interrupt controller */ + s->irqs = s3c24xx_irq_init(s, CPU_S3C2440X_IRQ_BASE); + + /* clock and power control */ + s3c24xx_clkcon_init(s, CPU_S3C2440X_CLKCON_BASE); + + /* PWM control used for timers */ + s3c24xx_timers_init(s, CPU_S3C2440X_TIMERS_BASE); + + /* And some GPIO */ + s3c24xx_gpio_init(s, CPU_S3C2440X_GPIO_BASE, CPU_S3C2440X_IDENT_S3C2440A); + + /* Serial ports */ + s3c24xx_serial_init(s, 0, CPU_S3C2440X_SERIAL_BASE); + s3c24xx_serial_init(s, 1, CPU_S3C2440X_SERIAL_BASE); + s3c24xx_serial_init(s, 2, CPU_S3C2440X_SERIAL_BASE); + + /* RTC for time */ + s3c24xx_rtc_init(s, CPU_S3C2440X_RTC_BASE); + + /* And some IIC */ + s3c24xx_iic_init(s, CPU_S3C2440X_IIC_BASE); + + /* A two port OHCI controller on IRQ 26 */ + usb_ohci_init_pxa(CPU_S3C2440X_OHCI, 2, -1, s->irqs[26]); + + /* LCD controller */ + s->lcd = s3c24xx_lcd_init(CPU_S3C2440X_LCD_BASE, s->irqs[16]); + + /* NAND controller */ + s3c24xx_nand_init(s, CPU_S3C2440X_NAND_BASE); + return s; +} + diff -urN qemusvnclean/hw/s3c2440x.h qemusvnpatches/hw/s3c2440x.h --- qemusvnclean/hw/s3c2440x.h 1970-01-01 01:00:00.000000000 +0100 +++ qemusvnpatches/hw/s3c2440x.h 2009-04-23 17:25:05.000000000 +0100 @@ -0,0 +1,30 @@ +/* hw/s3c2440x.h + * + * Samsung s3c2440x cpu register definitions + * + * Copyright 2006, 2007, 2008 Daniel Silverstone and Vincent Sanders + * + * This file is under the terms of the GNU General Public + * License Version 2. + */ + +#ifndef S3C2440X_H +#define S3C2440X_H 1 + +#include "s3c24xx.h" + +/* S3C2440 Physical memory areas */ + +/* Chip select 0 */ +#define CPU_S3C2440X_CS0 (0x00000000) +#define CPU_S3C2440X_CS1 (0x08000000) +#define CPU_S3C2440X_CS2 (0x10000000) +#define CPU_S3C2440X_CS3 (0x18000000) +#define CPU_S3C2440X_CS4 (0x20000000) +#define CPU_S3C2440X_CS5 (0x28000000) +#define CPU_S3C2440X_RAM (0x30000000) + +/* s3c2440 SOC initialisation */ +S3CState *s3c2440x_init(int sdram_size); + +#endif /* S3C2440X_H */ -- Regards Vincent http://www.kyllikki.org/