From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Lza4u-0002W0-3z for qemu-devel@nongnu.org; Thu, 30 Apr 2009 13:29:44 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Lza4p-0002NK-Gh for qemu-devel@nongnu.org; Thu, 30 Apr 2009 13:29:43 -0400 Received: from [199.232.76.173] (port=54348 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Lza4p-0002N9-Da for qemu-devel@nongnu.org; Thu, 30 Apr 2009 13:29:39 -0400 Received: from bsdimp.com ([199.45.160.85]:61221 helo=harmony.bsdimp.com) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Lza4o-0008Q6-Pl for qemu-devel@nongnu.org; Thu, 30 Apr 2009 13:29:39 -0400 Date: Thu, 30 Apr 2009 11:28:20 -0600 (MDT) Message-Id: <20090430.112820.48552365.imp@bsdimp.com> Subject: Re: [Qemu-devel] Re: questions on default_config_write in hw/pci.c From: "M. Warner Losh" In-Reply-To: <20090430171526.GA10638@amt.cnet> References: <20090430161508.GA15893@redhat.com> <20090430171526.GA10638@amt.cnet> Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: mtosatti@redhat.com Cc: qemu-devel@nongnu.org, aliguori@us.ibm.com, avi@redhat.com, mst@redhat.com In message: <20090430171526.GA10638@amt.cnet> Marcelo Tosatti writes: : On Thu, Apr 30, 2009 at 07:15:08PM +0300, Michael S. Tsirkin wrote: : > Hi, : > I've been looking at hw/pci.c, specifically at how config : > read/write are implemented, and have a couple of questions : > about default_config_write: : > : > 1. The code at the beginning (if len == 4 ...) : > seems to only update pci base registers if a dword write : > is performed. I think it's legal for the guest to perform 4 : > single-byte writes. Should this be supported? : > : > 2. The large switch statement at the end of this function : > uses hard-coded register offsets. Would it make sense : > to change it to use macros from hw/pci.h? : > : > 3. Still there I see: : > switch(d->config[0x0e]) { : > case 0x00: : > case 0x80: : > register 0x0e is header type, which has defined values : > of 0x00 (device or host bridge), 0x01 (pci to pci bridge) and : > 0x02 (cardbus bridge). What is 0x80 and when is it used? : > Would it make sense to remove this? : : Don't know. Check the PCI spec? The above is a bug. 0x80 is a bit that says "I have multiple functions" and is orthogonal to the type of device. : > switch(d->config[0x0e]) { should be switch(d->config[0x0e] & 0x7f) { : > 4. Still there, there's some handling done for type 1 devices. : > This support seems imcomplete. : > Are there any PCI-to-PCI bridges emulated by qemu? : > Would it make sense to remove this code? : : : It did work at one point: : : http://www.mail-archive.com/kvm-devel@lists.sourceforge.net/msg16647.html I have vague plans to do Cardbus-to-PCI bridge at some point... Warner