From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Lzttp-0006Xn-EE for qemu-devel@nongnu.org; Fri, 01 May 2009 10:39:37 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Lzttk-0006L3-HJ for qemu-devel@nongnu.org; Fri, 01 May 2009 10:39:36 -0400 Received: from [199.232.76.173] (port=52763 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Lzttk-0006Kg-Ch for qemu-devel@nongnu.org; Fri, 01 May 2009 10:39:32 -0400 Received: from mx20.gnu.org ([199.232.41.8]:9996) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Lzttk-0002VN-4u for qemu-devel@nongnu.org; Fri, 01 May 2009 10:39:32 -0400 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Lzttj-0001vv-De for qemu-devel@nongnu.org; Fri, 01 May 2009 10:39:31 -0400 From: Paul Brook Subject: Re: [Qemu-devel] [PATCH] 64 bit I/O support v7 Date: Fri, 1 May 2009 15:39:28 +0100 References: <49EDB109.5010009@earthlink.net> <200905011303.50885.paul@codesourcery.com> <49FB0663.8050009@earthlink.net> In-Reply-To: <49FB0663.8050009@earthlink.net> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200905011539.29209.paul@codesourcery.com> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Robert Reif Cc: qemu-devel@nongnu.org > Hardware that supports reading 2 32 bit registers with one 64 > bit access can have the 64 callback do 2 32 bit accesses. Doesn't this include most PCI devices? Paul