From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1M1Nuq-0004Jn-S4 for qemu-devel@nongnu.org; Tue, 05 May 2009 12:54:48 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1M1Num-0004GT-98 for qemu-devel@nongnu.org; Tue, 05 May 2009 12:54:48 -0400 Received: from [199.232.76.173] (port=47827 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1M1Num-0004GD-0L for qemu-devel@nongnu.org; Tue, 05 May 2009 12:54:44 -0400 Received: from smtp.mailix.net ([216.148.213.132]:45172) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_3DES_EDE_CBC_SHA1:24) (Exim 4.60) (envelope-from ) id 1M1Nul-0000Rt-Bi for qemu-devel@nongnu.org; Tue, 05 May 2009 12:54:43 -0400 Received: from [70.124.59.121] (helo=shadowfax.no-ip.com) by smtp.mailix.net with asmtp (Exim 4.24-H) id 1M1O0z-0000ZF-Vp for qemu-devel@nongnu.org; Tue, 05 May 2009 10:01:10 -0700 Received: from [97.77.182.214] ([97.77.182.214]) by shadowfax.no-ip.com (Kerio MailServer 6.6.0 patch 1) for qemu-devel@nongnu.org; Tue, 5 May 2009 11:54:30 -0500 From: "Adnan Khaleel" Message-ID: <20090505165430.dece2585@shadowfax.no-ip.com> Date: Tue, 05 May 2009 11:54:30 -0500 MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="-----------19fe5d7f5b0ee5e0e32d07b23006fa38" Subject: [Qemu-devel] Question about adding new instructions to Qemu Reply-To: adnan@khaleel.us List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This is a multi-part message in MIME format. -------------19fe5d7f5b0ee5e0e32d07b23006fa38 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hello Developers, I plan on using Qemu on a research project and I wanted some feedback fr= om you guys before I started making some changes. 1. I plan on using Qemu as a functional front end to a cycle accurate ba= ck end. Essentially what I would like to do is have qemu-system-x86=5F64= run at full speed i.e with translation cache enabled until it reaches s= ome point of interest in my benchmark. At that point, I would like to di= sable the translation cache and have qemu single step through the instru= ctions. Looking through the source I see a "singlestep" mode which I thi= nk does what I need. Can anybody comment and tell me if this is indeed c= orrect=3F 2. I'll also need to examine my guests physical memory periodically. Is = the function cpu=5Fphysical=5Fmemory=5Frw the correct way to do this=3F 3. I'm still getting familiar with the code, especially the dynamic tran= slation part of it. I've been trying to understand translate.c to see ho= w this is actually done and I'm a bit lost. I'm specifically looking at = x86=5F64 target running on a x86=5F64 host. What I'd ultimately like to = do is add new instructions to my target cpu=3F How can I do that=3F I've= read all the documentation thats on the website and it looks like a lot= of that is out of date since the Usenix paper refers to dyngen and it s= eems like Qemu now uses tcg to perform this purpose. If somebody could e= xplain with a simple example with say mov or add, that would go a long w= ay in helping me understand how the breakup into uops is done and untima= tely how the translation into host instructions happens. It seems like e= verything seems like each translation ends up with=20 *gen=5Fopc=5Fptr++ =3D opc; *gen=5Fopparam=5Fptr++ =3D arg1; and I can't understand the underlying magic. 4. I'm also trying to get qemu-system-x86=5F64 to boot SuSE 10 as a gues= t OS with 128 cores and I haven't had any luck getting the system to boo= t with more than 48 cores. In failsafe mode I can get 64 cores. I know Q= emu supports upto 255 cores so I was wondering if any developers have an= y experience in simulating a large number of cores. Any pointers to a pa= rticular linux distribution, kernel version or command line options woul= d be extremely helpful. Thanks in advance, -AK -------------19fe5d7f5b0ee5e0e32d07b23006fa38 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hello Developers,

I plan on using Qemu on a research project and = I wanted some feedback from you guys before I started making some change= s.

1. I plan on using Qemu as a functional front end to a cycle a= ccurate back end. Essentially what I would like to do is have qemu-syste= m-x86=5F64 run at full speed i.e with translation cache enabled until it= reaches some point of interest in my benchmark. At that point, I would = like to disable the translation cache and have qemu single step through = the instructions. Looking through the source I see a "singlestep" mode which I think does what I need.= Can anybody comment and tell me if this is indeed correct=3F

2. = I'll also need to examine my guests physical memory periodically. Is the= function cpu=5Fphysical=5Fmemory=5Frw the correct way to do this=3F=

3. I'm still getting familiar with the code, especially the dyna= mic translation part of it. I've been trying to understand translate.c t= o see how this is actually done and I'm a bit lost. I'm specifically loo= king at x86=5F64 target running on a x86=5F64 host. What I'd ultimately = like to do is add new instructions to my target cpu=3F How can I do that=3F I've read all the document= ation thats on the website and it looks like a lot of that is out of dat= e since the Usenix paper refers to dyngen and it seems like Qemu now use= s tcg to perform this purpose. If somebody could explain with a simple e= xample with say mov or add, that would go a long way in helping me under= stand how the breakup into uops is done and untimately how the translati= on into host instructions happens. It seems like everything seems like e= ach translation ends up with

    *gen=5Fopc=5Fptr= ++ =3D opc;
    *gen=5Fopparam=5Fptr++ =3D arg1;
and I can't understand the underlying magic.

4. I'm also trying= to get qemu-system-x86=5F64 to boot SuSE 10 as a guest OS with 128 core= s and I haven't had any luck getting the system to boot with more than 4= 8 cores. In failsafe mode I can get 64 cores. I know Qemu supports upto = 255 cores so I was wondering if any developers have any experience in simulating a large number of cores. Any pointers to a particular linux distribution, kernel version or c= ommand line options would be extremely helpful.

Thanks in advance= ,

-AK
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