From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1M224S-0002dl-T5 for qemu-devel@nongnu.org; Thu, 07 May 2009 07:47:25 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1M224O-0002Y4-9k for qemu-devel@nongnu.org; Thu, 07 May 2009 07:47:24 -0400 Received: from [199.232.76.173] (port=55330 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1M224N-0002XT-Ku for qemu-devel@nongnu.org; Thu, 07 May 2009 07:47:19 -0400 Received: from mx2.redhat.com ([66.187.237.31]:41102) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1M224N-0000Pf-4u for qemu-devel@nongnu.org; Thu, 07 May 2009 07:47:19 -0400 Date: Thu, 7 May 2009 14:46:09 +0300 From: "Michael S. Tsirkin" Subject: Re: [Qemu-devel] Re: pci_default_config_write() clean up. Message-ID: <20090507114609.GH32039@redhat.com> References: <20090507084019.GA25512%yamahata@valinux.co.jp> <20090507092908.GC32039@redhat.com> <20090507095540.GC25512%yamahata@valinux.co.jp> <20090507102538.GF32039@redhat.com> <20090507111351.GD25512%yamahata@valinux.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090507111351.GD25512%yamahata@valinux.co.jp> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Isaku Yamahata Cc: mtosatti@redhat.com, qemu-devel@nongnu.org, armbru@redhat.com On Thu, May 07, 2009 at 08:13:51PM +0900, Isaku Yamahata wrote: > On Thu, May 07, 2009 at 01:25:38PM +0300, Michael S. Tsirkin wrote: > > > How about callback? > > > > Yes, I think callbacks have the potential to simplify code. > > Would you like to add them on top of my patch then? > > Okay. > > > - There's some tricky code there to trigger callbacks only once > > on a multibyte transaction. It would be simpler just to have per-dword > > callbacks. These could get the mask of the written-to bytes and do > > if (written_mask & interesting_mask) > > stuff > > Are you assuming that word/dword io port access is word/dword aligned? I think this does not have to be the case in I/O generally. However I think that configuration cycles specifically can never cross a dword boundary (and if they could, I think that PCI spec does not define any registers that cross dword boundary). I found this in the PCI spec: Register Number is an encoded value used to select a DWORD in the Configuration Space of the intended target. -- MST