* [Qemu-devel] [PATCH 2/2] fix ARMv7 data processing instructions
@ 2009-05-06 6:16 Juha Riihimäki
2009-05-15 2:05 ` Paul Brook
0 siblings, 1 reply; 3+ messages in thread
From: Juha Riihimäki @ 2009-05-06 6:16 UTC (permalink / raw)
To: qemu-devel
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ARMv7 defines a new behavior for ARM data processing instructions
compared to earlier architecture revisions; when the destination
register is R15, a Branch and Exchange operation is executed rather
than a simple Branch to the target address. This patch corrects the
behavior of the emulation for the aforementioned operations. To be
applied after applying the previous patch in this patch set.
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
---
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diff --git a/target-arm/translate.c b/target-arm/translate.c
index 4441c8d..2c97606 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -821,6 +821,19 @@ static inline void gen_bx_T0(DisasContext *s)
gen_bx(s, tmp);
}
+/* Variant of store_reg which uses branch&exchange logic when storing
+ to r15 in ARM architecture v7 and above. The source must be a temporary
+ and will be marked as dead. */
+static inline void store_reg_bx(CPUState *env, DisasContext *s,
+ int reg, TCGv var)
+{
+ if (reg == 15 && ENABLE_ARCH_7) {
+ gen_bx(s, var);
+ } else {
+ store_reg(s, reg, var);
+ }
+}
+
static inline TCGv gen_ld8s(TCGv addr, int index)
{
TCGv tmp = new_tmp();
@@ -6128,13 +6141,13 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
tcg_gen_and_i32(tmp, tmp, tmp2);
if (logic_cc)
gen_logic_CC(tmp);
- store_reg(s, rd, tmp);
+ store_reg_bx(env, s, rd, tmp);
break;
case 0x01:
tcg_gen_xor_i32(tmp, tmp, tmp2);
if (logic_cc)
gen_logic_CC(tmp);
- store_reg(s, rd, tmp);
+ store_reg_bx(env, s, rd, tmp);
break;
case 0x02:
if (set_cc && rd == 15) {
@@ -6148,7 +6161,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
gen_helper_sub_cc(tmp, tmp, tmp2);
else
tcg_gen_sub_i32(tmp, tmp, tmp2);
- store_reg(s, rd, tmp);
+ store_reg_bx(env, s, rd, tmp);
}
break;
case 0x03:
@@ -6156,35 +6169,35 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
gen_helper_sub_cc(tmp, tmp2, tmp);
else
tcg_gen_sub_i32(tmp, tmp2, tmp);
- store_reg(s, rd, tmp);
+ store_reg_bx(env, s, rd, tmp);
break;
case 0x04:
if (set_cc)
gen_helper_add_cc(tmp, tmp, tmp2);
else
tcg_gen_add_i32(tmp, tmp, tmp2);
- store_reg(s, rd, tmp);
+ store_reg_bx(env, s, rd, tmp);
break;
case 0x05:
if (set_cc)
gen_helper_adc_cc(tmp, tmp, tmp2);
else
gen_add_carry(tmp, tmp, tmp2);
- store_reg(s, rd, tmp);
+ store_reg_bx(env, s, rd, tmp);
break;
case 0x06:
if (set_cc)
gen_helper_sbc_cc(tmp, tmp, tmp2);
else
gen_sub_carry(tmp, tmp, tmp2);
- store_reg(s, rd, tmp);
+ store_reg_bx(env, s, rd, tmp);
break;
case 0x07:
if (set_cc)
gen_helper_sbc_cc(tmp, tmp2, tmp);
else
gen_sub_carry(tmp, tmp2, tmp);
- store_reg(s, rd, tmp);
+ store_reg_bx(env, s, rd, tmp);
break;
case 0x08:
if (set_cc) {
@@ -6214,7 +6227,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
tcg_gen_or_i32(tmp, tmp, tmp2);
if (logic_cc)
gen_logic_CC(tmp);
- store_reg(s, rd, tmp);
+ store_reg_bx(env, s, rd, tmp);
break;
case 0x0d:
tcg_gen_mov_i32(tmp, tmp2);
@@ -6224,7 +6237,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
goto illegal_op;
gen_exception_return(s, tmp);
} else {
- store_reg(s, rd, tmp);
+ store_reg_bx(env, s, rd, tmp);
if (logic_cc)
gen_logic_CC(tmp2);
}
@@ -6233,14 +6246,14 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
tcg_gen_bic_i32(tmp, tmp, tmp2);
if (logic_cc)
gen_logic_CC(tmp);
- store_reg(s, rd, tmp);
+ store_reg_bx(env, s, rd, tmp);
break;
default:
case 0x0f:
tcg_gen_not_i32(tmp, tmp2);
if (logic_cc)
gen_logic_CC(tmp);
- store_reg(s, rd, tmp);
+ store_reg_bx(env, s, rd, tmp);
break;
}
dead_tmp(tmp2);
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^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [Qemu-devel] [PATCH 2/2] fix ARMv7 data processing instructions
2009-05-06 6:16 [Qemu-devel] [PATCH 2/2] fix ARMv7 data processing instructions Juha Riihimäki
@ 2009-05-15 2:05 ` Paul Brook
2009-05-15 2:19 ` Paul Brook
0 siblings, 1 reply; 3+ messages in thread
From: Paul Brook @ 2009-05-15 2:05 UTC (permalink / raw)
To: qemu-devel; +Cc: Juha Riihimäki
On Wednesday 06 May 2009, Juha Riihimäki wrote:
> ARMv7 defines a new behavior for ARM data processing instructions
> compared to earlier architecture revisions; when the destination
> register is R15, a Branch and Exchange operation is executed rather
> than a simple Branch to the target address. This patch corrects the
> behavior of the emulation for the aforementioned operations.
We should not switch modes if instructions sets the condition flags.
Paul
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH 2/2] fix ARMv7 data processing instructions
2009-05-15 2:05 ` Paul Brook
@ 2009-05-15 2:19 ` Paul Brook
0 siblings, 0 replies; 3+ messages in thread
From: Paul Brook @ 2009-05-15 2:19 UTC (permalink / raw)
To: qemu-devel; +Cc: Juha Riihimäki
On Friday 15 May 2009, Paul Brook wrote:
> On Wednesday 06 May 2009, Juha Riihimäki wrote:
> > ARMv7 defines a new behavior for ARM data processing instructions
> > compared to earlier architecture revisions; when the destination
> > register is R15, a Branch and Exchange operation is executed rather
> > than a simple Branch to the target address. This patch corrects the
> > behavior of the emulation for the aforementioned operations.
>
> We should not switch modes if instructions sets the condition flags.
On second looks, we get those cases wrong anyway, so I've applied the patch.
Paul
^ permalink raw reply [flat|nested] 3+ messages in thread
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2009-05-06 6:16 [Qemu-devel] [PATCH 2/2] fix ARMv7 data processing instructions Juha Riihimäki
2009-05-15 2:05 ` Paul Brook
2009-05-15 2:19 ` Paul Brook
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