Re: [Qemu-devel] [PATCH 02/15] S3C system on chip integrated peripheral device state header

[Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>]

> +    uint32_t tclk1; /* second timer clock source frequency */
> +
> +    /* GPIO block */
> +    uint32_t gpio_reg[47];
> +
> +    /* Realtime clock */
> +    uint8_t rtc_reg[19];
> +
> +    /* i2c */
> +    struct s3c24xx_i2c_state_s *iic;
> +    
> +    /* Timers, (Specifically timer4) */
> +    uint32_t timers_reg[17];
it will be better to define a struct with the timers_reg content
same with the other arry
> +    QEMUTimer *timer4;
> +    uint32_t timer4_reload_value;
> +    int64_t timer4_last_ticked;
> +
> +    /* LCD controller */
> +    struct s3c24xx_lcd_state_s *lcd;
> +
> +    /* NAND controller, and chip attached */
> +    uint32_t nand_reg[5];
> +    struct nand_flash_s *nand_chip;
> +} S3CState;
Best Regards,
J.