From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1M6L8n-00086q-0s for qemu-devel@nongnu.org; Tue, 19 May 2009 04:57:41 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1M6L8h-00084M-RM for qemu-devel@nongnu.org; Tue, 19 May 2009 04:57:39 -0400 Received: from [199.232.76.173] (port=47047 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1M6L8h-00084J-Mw for qemu-devel@nongnu.org; Tue, 19 May 2009 04:57:35 -0400 Received: from mx2.redhat.com ([66.187.237.31]:33387) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1M6L8h-0004je-7W for qemu-devel@nongnu.org; Tue, 19 May 2009 04:57:35 -0400 Date: Tue, 19 May 2009 11:56:32 +0300 From: "Michael S. Tsirkin" Subject: Re: [Qemu-devel] [PATCH] qemu: cleanup default_write_config Message-ID: <20090519085632.GA29160@redhat.com> References: <20090503220122.GA25047@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090503220122.GA25047@redhat.com> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, Anthony Liguori , Blue Swirl , mtosatti@redhat.com, armbru@redhat.com On Mon, May 04, 2009 at 01:01:22AM +0300, Michael S. Tsirkin wrote: > Change pci default write config to use symbolic constants and a table-driven > design: add a mask table with writable bits set and readonly bits unset. > This makes it much easier to support multi-byte registers. > > As a result, writing a single byte in BAR registers now works as > it should. Writing to upper limit registers in the bridge > also works as it should. Code is also shorter. > > Signed-off-by: Michael S. Tsirkin Any feedback on this patch? I'd like to use mask table as the basis for MSI integration work (setting up appropriate masks for capability bits) and if there are issues with this approach, I'd like to know. -- MST