From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43)
	id 1M6Q2n-0004nd-HS
	for qemu-devel@nongnu.org; Tue, 19 May 2009 10:11:49 -0400
Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43)
	id 1M6Q2i-0004mk-4D
	for qemu-devel@nongnu.org; Tue, 19 May 2009 10:11:48 -0400
Received: from [199.232.76.173] (port=48508 helo=monty-python.gnu.org)
	by lists.gnu.org with esmtp (Exim 4.43) id 1M6Q2i-0004mh-1E
	for qemu-devel@nongnu.org; Tue, 19 May 2009 10:11:44 -0400
Received: from mx2.redhat.com ([66.187.237.31]:46045)
	by monty-python.gnu.org with esmtp (Exim 4.60)
	(envelope-from <mtosatti@redhat.com>) id 1M6Q2h-0005bl-Ga
	for qemu-devel@nongnu.org; Tue, 19 May 2009 10:11:43 -0400
Date: Tue, 19 May 2009 11:11:04 -0300
From: Marcelo Tosatti <mtosatti@redhat.com>
Subject: Re: [Qemu-devel] [PATCH] qemu: cleanup default_write_config
Message-ID: <20090519141104.GA4859@amt.cnet>
References: <20090503220122.GA25047@redhat.com>
	<20090519085632.GA29160@redhat.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <20090519085632.GA29160@redhat.com>
List-Id: qemu-devel.nongnu.org
List-Unsubscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.gnu.org/pipermail/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Blue Swirl <blauwirbel@gmail.com>, qemu-devel@nongnu.org, armbru@redhat.com

On Tue, May 19, 2009 at 11:56:32AM +0300, Michael S. Tsirkin wrote:
> On Mon, May 04, 2009 at 01:01:22AM +0300, Michael S. Tsirkin wrote:
> > Change pci default write config to use symbolic constants and a table-driven
> > design: add a mask table with writable bits set and readonly bits unset.
> > This makes it much easier to support multi-byte registers.
> > 
> > As a result, writing a single byte in BAR registers now works as
> > it should. Writing to upper limit registers in the bridge
> > also works as it should. Code is also shorter.
> > 
> > Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> 
> Any feedback on this patch?
> I'd like to use mask table as the basis for MSI integration work (setting
> up appropriate masks for capability bits) and if there are issues with
> this approach, I'd like to know.

Don't see any problem with it.