From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1M76yI-0000lC-Fa for qemu-devel@nongnu.org; Thu, 21 May 2009 08:02:02 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1M76yD-0000hy-M2 for qemu-devel@nongnu.org; Thu, 21 May 2009 08:02:01 -0400 Received: from [199.232.76.173] (port=43894 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1M76yD-0000hl-AP for qemu-devel@nongnu.org; Thu, 21 May 2009 08:01:57 -0400 Received: from mx20.gnu.org ([199.232.41.8]:50508) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1M76yC-0007Xh-RB for qemu-devel@nongnu.org; Thu, 21 May 2009 08:01:56 -0400 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1M76yA-0000xx-Lo for qemu-devel@nongnu.org; Thu, 21 May 2009 08:01:54 -0400 From: Paul Brook Subject: Re: [Qemu-devel] [PATCH] qemu: msi irq allocation api Date: Thu, 21 May 2009 13:01:50 +0100 References: <20090520162130.GA22109@redhat.com> <200905211134.21184.paul@codesourcery.com> <4A15346C.8090906@redhat.com> In-Reply-To: <4A15346C.8090906@redhat.com> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200905211301.52089.paul@codesourcery.com> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Carsten Otte , kvm@vger.kernel.org, "Michael S. Tsirkin" , Rusty Russell , virtualization@lists.linux-foundation.org, Christian Borntraeger , Avi Kivity > >> The PCI bus doesn't need any special support (I think) but something on > >> the other end needs to interpret those writes. > > > > Sure. But there's definitely nothing PCI specific about it. I assumed > > this would all be contained within the APIC. > > MSIs are defined by PCI and their configuration is done using the PCI > configuration space. A MSI is just a regular memory write, and the PCI spec explicitly states that a target (e.g. the APIC) is unable to distinguish between a MSI and any other write. The PCI config bits just provide a way of telling the device where/what to write. > >> In any case we need some internal API for this, and qemu_irq looks like > >> a good choice. > > > > What do you expect to be using this API? > > virtio, emulated devices capable of supporting MSI (e1000?), device > assignment (not yet in qemu.git). It probably makes sense to have common infrastructure in pci.c to expose/implement device side MSI functionality. However I see no need for a direct API between the device and the APIC. We already have an API for memory accesses and MMIO regions. I'm pretty sure a system could implement MSI by pointing the device at system ram, and having the CPU periodically poll that. Paul