From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1M792k-000122-RC for qemu-devel@nongnu.org; Thu, 21 May 2009 10:14:46 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1M792g-00010H-7c for qemu-devel@nongnu.org; Thu, 21 May 2009 10:14:46 -0400 Received: from [199.232.76.173] (port=34170 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1M792f-000107-QH for qemu-devel@nongnu.org; Thu, 21 May 2009 10:14:42 -0400 Received: from mx20.gnu.org ([199.232.41.8]:60646) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1M792f-0005i4-9O for qemu-devel@nongnu.org; Thu, 21 May 2009 10:14:41 -0400 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1M792X-0002Y8-Em for qemu-devel@nongnu.org; Thu, 21 May 2009 10:14:33 -0400 From: Paul Brook Subject: Re: [Qemu-devel] [PATCH] qemu: msi irq allocation api Date: Thu, 21 May 2009 15:14:30 +0100 References: <20090520162130.GA22109@redhat.com> <200905211453.14691.paul@codesourcery.com> <4A155EC6.6070501@redhat.com> In-Reply-To: <4A155EC6.6070501@redhat.com> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200905211514.31059.paul@codesourcery.com> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Carsten Otte , kvm@vger.kernel.org, "Michael S. Tsirkin" , Rusty Russell , virtualization@lists.linux-foundation.org, Christian Borntraeger , Avi Kivity On Thursday 21 May 2009, Avi Kivity wrote: > Paul Brook wrote: > >>> which is a trivial wrapper around stl_phys. > >> > >> OK, but I'm adding another level of indirection in the middle, > >> to allow us to tie in a kvm backend. > > > > kvm has no business messing with the PCI device code. > > kvm has a fast path for irq injection. If qemu wants to support it we > need some abstraction here. Fast path from where to where? Having the PCI layer bypass/re-implement the APIC and inject the interrupt directly into the cpu core sounds a particularly bad idea. Paul